Jaeyong Jeong

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

A read-disturb management technique for high-density NAND flash memory

The read-disturb problem is emerging as one of the main reliability issues for future high-density NAND flash memory. A read-disturb error, which causes data loss, occurs to data in a page when a large number of reads are performed to its neighboring pages in the same block. In this paper, we propose a novel read-disturb management technique which reduces the frequency of expensive data migrations needed for avoiding read-disturb errors. Our technique proactively converts highly skewed read accesses to a small number of blocks into more balanced read accesses to a large number of blocks by intelligently changing data block locations accessed. Our experimental results show that our technique is effective in handling the read-disturb problem, reducing the time overhead of data migrations on average by 50% over an FTL based on the existing read-disturb management technique.

Improving performance and lifetime of NAND storage systems using relaxed program sequence

We propose a new system-level solution that improves both the performance and lifetime of NAND storage systems by exploiting the performance asymmetry of NAND devices. At the device level, we propose a new program sequence, called relaxed program sequence (RPS), which allows more flexible page allocations in a block without compromising NAND reliability. By combining RPS with per-block parity pages, we can improve the write bandwidth and eliminate expensive paired page backup operations. Experimental results show that the proposed technique can increase IOPS by up to 56% and reduce the number of block erasures by up to 30% over an existing RPS-oblivious FTL.

An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory

The read-disturb problem is emerging as one of the main reliability issues in high-density NAND flash memory. A read-disturb error, which causes data loss, occurs to a page when a large number of reads are performed to its neighboring pages. In this paper, we propose a novel integrated approach for managing the read-disturb problem. Our approach is based on our key observations from the NAND physics that the read disturbance to neighboring pages is a function of the read voltage and the read time. Since the read disturbance has an exponential dependence on the read voltage, lowering the read voltage can improve the read-disturb resistance of a NAND block. By modifying NAND chips to support multiple read modes with different read voltages, our approach allows a flash translation layer module to exploit the tradeoff between the read disturbance and write speed. Since the read disturbance is also proportional to the read time, our approach exploits the difference in the read time among different NAND pages so that frequently read pages can be less intensively read-disturbed using fast page reads. By intelligently relocating read-intensive data to read-disturb resistant blocks and pages, our approach can reduce a large portion of the time overhead from managing read-disturb errors. We also propose a proactive data migration technique which is effective in reducing large variations in I/O response times of the existing on-demand read reclaim (RR) technique. Our experimental results show that our proposed techniques can reduce the execution time overhead by 73% over the existing read-disturb management technique while reducing I/O response time fluctuations during RR activations.

Flashdefibrillator: a data recovery technique for retention failures in NAND flash memory

Although NAND flash memory is known as a nonvolatile memory device, the non-volatility of the data stored in the NAND flash memory is guaranteed only for a specified retention time. Since the NAND retention time assumes specific operation conditions, when the NAND flash memory is exposed to an abnormal environment beyond the specified operation conditions, stored data cannot be reliably retrieved due to retention failures. In this paper, we propose a novel data recovery technique, called FlashDefibrillator (FD), for recovering retention failures in recent NAND flash memory. By reversely exploiting charge-transient behavior observed in recent 20-nm node (or below) NAND flash memory, FD can identify retention-failed cells in a progressive fashion using a novel selective error-correction procedure. FD repeatedly applies the selective error-correction procedure until retention failures are fully recovered. Our measurement results with recent 20-nm node NAND chips show that FD outperforms the existing recovery technique in both the data recovery speed and the data recovery capability. FD can recover retention failures up to 23 times faster over the existing data recovery technique. Furthermore, FD can successfully recover severely retention-failed data (such as ones experienced eight times longer retention times than the retention-time specification) which were not recoverable with the existing technique.

Dynamic Erase Voltage and Time Scaling for Extending Lifetime of NAND Flash-Based SSDs

The decreasing lifetime of NAND flash memory, as a side effect of recent advanced semiconductor process scaling, is emerging as one of major barriers to the wide adoption of SSDs in high-performance computing systems. In this paper, we propose Dynamic Erase Voltage and Time Scaling (DeVTS), an integrated approach to extend the lifetime (particularly, endurance) of NAND flash memory. DeVTS is motivated by our key observation that erasing a NAND block with a lower voltage or at a slower speed can significantly improve NAND endurance. However, using a lower erase voltage causes adverse side effects on the write performance and retention capability of NAND flash memory. In order to improve NAND endurance without affecting the other NAND requirements, we take advantage of idle times between write requests and variations of the retention requirement when writing data to a NAND block erased with a lower voltage. We have implemented a DeVTS-aware FTL, called dvsFTL, which exploits the tradeoff relationship between the endurance and erase voltages/times by accurately predicting the write performance and retention requirements. Our experimental results show that dvsFTL can improve NAND endurance by 94 percent, on average, over an existing DeVTS-unaware FTL while all the NAND requirements are preserved.