Youngsun Song

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

Improving Read Disturb Characteristics by Self-Boosting Read Scheme for Multilevel NAND Flash Memories

A new NAND string and its read operation scheme using self-boosting as a solution for improving read disturb characteristics of NAND flash memories are proposed. By using the proposed self-boosting read scheme, which includes an optimized bias voltage and adjusted threshold voltage (Vth) of dummy cells, the self-boosted channel voltage prevents soft-programming in unselected memory cells during read operation due to reduced electric field across tunnel oxide. Compared to the conventional scheme this leads to a significant improvement in read disturb characteristics. From simulation and measurement results, the worst electric field of the proposed NAND flash memory during read operation is decreased by around 50% and Vth shifts caused by read disturb is lowered by around 40%, compared to conventional NAND. The proposed NAND was fabricated in a 60 nm NAND technology and successfully demonstrated.

DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array

In this brief, we have investigated the program disturb characteristics caused by drain-induced barrier lowering (DIBL) in a 32-nm nand Flash memory device. It was found that the VTH shift of the (N + 2)th erased state cell is larger than that of the (N + 1)th erased state cell if it is assumed that the channel of the Nth cell is cut off. It is revealed that the cut off is caused by a cell-to-cell coupling effect that is becoming more severe in the development of high-density Flash memory arrays.

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

This paper presents an analytic model for NAND flash array where channel coupling embodies. Channel coupling effect which is becoming a more serious issue in developing high-density flash memory devices should be effectively suppressed. By applying the coupling model to a 30-nm NAND flash product, the simulation showed a good agreement with the measurement results. Also, complex problems in scaled NAND flash memories could be accurately explained by circuit simulations. This evaluation will be useful in developing high-density multi-level cell (MLC) NAND flash technologies.

Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption

Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristics beyond sub-30 nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those of conventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40 nm multi level cell (MLC) NAND device.

A Simple compact model for hot carrier injection phenomenon in 32 nm NAND flash memory device

In this work, a SPICE-friendly hot carrier injection (HCI) model for NAND flash memory has been proposed. By applying the HCI model to the 32 nm NAND product, the simulation based on HCI model showed good agreement with the measurement results. Based on the proposed model, a complex problem regarding the program disturbance in the scaled NAND flash memory array can be predicted through simple circuit simulations. Moreover, it is very useful in developing the ultra-short channel devices for high density multi-level cell (MLC) NAND flash technologies.

Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories

In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase memory cells are presented for achieving high program inhibition with lower program disturbance in sub-40 nm MLC NAND flash and beyond. Simple two-step dynamic Vpass control technique is used and over 40% program failure reduction after 30 k P/E cycling is achieved in the proposed scheme, compared to conventional method. A major pattern dependency of program disturbance in MLC NAND flash is also described in this paper. In order to achieve high immunity for the data pattern dependency in program disturbance, optimizing erase Vth and its distribution using ISPP-after-erase with a precise negative Vth sensing scheme are proposed. The proposed schemes are demonstrated using 42 nm MLC NAND flash test chip and about 2 times better Vpass window margin is obtained compared to conventional scheme.