Jagar Singh

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Continuous process-level and system-level innovation has driven Moores Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

Analog, RF, and ESD device challenges and solutions for 14nm FinFET technology and beyond

Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes, BJTs with poor ideality, mismatch, weak re-surf action and low drain current(Id/μm) of Laterally diffused MOS (LDMOS), degraded RF and 1/f noise of analog CMOS, etc. Innovative solutions which maintain process simplicity and low cost are described in this paper. These new device designs demonstrate excellent performance, such as near perfect-ideality(η)≈1.01 diodes, low leakage, high BV, and BJTs with excellent analog behavior. Fin-based LDMOS and ESD devices outperform conventional planar devices in terms of Id/μm and ESD human body model (HBM) performance, respectively.

14nm FinFET technology for analog and RF applications

This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be seen in the self-gain (Gm/Gds), which shows a significant increase to 40 and 34 for NFET and PFET respectively. Superior 1/f noise of 17/35 f(V∗μm)2/Hz @ 1KHz for N/PFET respectively is also achieved. To extend further low voltage operation and power saving, ultra-low Vt devices are also developed. Furthermore, a deep N-well (triple well) process is introduced to improve the ultra-low signal immunity from substrate noise, while offering useful devices like VNPN and high breakdown voltage deep N-well diodes. A superior Ft/Fmax, high self-gain, low 1/f noise and substrate isolation characteristics truly extend the capability of the 14nm FinFETs for analog and RF applications.

Methodology to achieve planar technology-like ESD performance in FINFET process

Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep implants. The selected ESD devices in Finfet process show competitive ESD performance without any significant cost adder.

Impact of wafer thinning on High-K Metal Gate 20nm devices

In this paper, the impact of wafer thinning on 20nm High K Metal Gate (HKMG) technology is evaluated. Fully fabricated test wafers are thinned down to well below 100μm, into the range required for 3D integration. The impact on NMOS and PMOS device performance parameters; channel current and threshold voltage (Vt) is investigated. Device reliability is monitored using NBTI (negative bias temperature instability) measurements. It is found that wafer thinning has negligible impact on Vt of I/O devices. However, we have seen a small impact on the channel leakage, and a moderate impact on saturation currents of high performance core devices. The channel current is reduced ~5% for NMOS, while there is a ~10% enhancement in the PMOS device. Device reliability was assessed using NBTI and no degradation is seen on the devices. This confirms that the thinning did not impact the front end of line gate oxide integrity.