Mahadeva Iyer Natarajan

Impact of e-SiGe S/D processes on FinFET PFET TDDB reliability

The impact of source/drain e-SiGe process engineering on time dependent dielectric breakdown (TDDB) on core PFETs fabricated with bulk FinFET technology is evaluated. It is observed that thicker e-SiGe buffer layer improves the PFETs TDDB. Electrical and physical analysis revealed that with thinner buffer layer, Ge atoms migrate to gate dielectric and accelerate the breakdown mechanisms due to poor surface roughness and stoichiometry. In addition, the process optimization of pre-baking of e-SiGe trench can also improve the TDDB even for relatively thinner buffer layer.

Methodology to achieve planar technology-like ESD performance in FINFET process

Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep implants. The selected ESD devices in Finfet process show competitive ESD performance without any significant cost adder.

Source of miscorrelation of product level HBM to TLP test results

Correlation between TLP and HBM test results at product level and/or complex ESD circuit is not feasible. In product level HBM testing there can be stress condition which is worse at low current compared to high ESD current. Such results cannot be replicated in TLP.

Reliability of 2T-core CMOS OTP non-volatile memory bitcells

Reliability assessment on 2T CMOS antifuse bitcell, consisting of two core NMOSFETs having a program transistor coupled in series with a select transistor, is presented. The discrepancy in the measured time to breakdown of program transistors and predicted minimum programming voltage by discrete device based time dependent dielectric breakdown model, is identified to be directly related to the select transistor sizing. In addition, the maximum programming voltage is controlled by junction leakage between the middle node of program/select transistors and substrate while the unprogramed/inhibit stage is in the programming stress. Using these two critical findings, for the first time, this paper presents a scientific frame work to aid designer and manufacturer to fine tune their design/process and produce robust memory elements and IP blocks.

ESD performance enhancement methodologies for CMOS power transistors

Key challenges in providing ESD protection for High Voltage CMOS technology is presented in this paper. Based on that, various methodologies to make the high voltage power transistor ESD self-protecting without changing the device IV characteristics and dimension, for different HV technologies is outlined.

Printed-circuit board (PCB) charge induced product yield-loss during the final test

The voltage to damage a chip under the ESD test is often higher than several hundred volts. However, we have observed that the voltage below 6V still can damage the chip to induce the yield-loss of a product in the production line. It is because that the voltage is high enough to damage the components of the low voltage circuits (1.8V), but is still too low to turn on the ESD protection device.