Marius K. Orlowski

Moderately doped channel multiple-finFET for logic applications

In this paper, moderately doped channel (MDC) multiple-FinFET is proposed and its electrical characteristics are investigated using 3D process and device, and 2D mixed-mode device and circuit simulation. It is shown that the MDC offers a better immunity to variations of the fin profile than the undoped channel for a short channel device, and Multiple-FinFET is critical for logic applications. The implementation of an asymmetrical doping profile further improves the performance of MDC Multiple-FinFET

Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?

Beyond 2007, when the channel length is projected to be 25 nm, effective scaling of classical planar bulk MOSFETs is expected to come to an end. Below 25 nm channel length, achieving adequate electrostatic control of short channel effects poses the most serious challenge. Non-classical double-gate, ultrathin-body transistors offer to minimize short-channel effects and allow for more aggressive scaling. Several three-dimensional (3-D) multigate structures such as FinFET, Trigate, MIGFET, ITFET have been demonstrated with good electrical characteristics down to gate lengths of 10 nm. The manufacturing of 3D devices is entirely compatible with the integration processes employed for planar CMOS MOSFETs. Provided that fabrication, yield, design, and cost issues can be rendered tractable, 3D devices are poised to breathe new life into Moore’s Law and close the gap between traditional CMOS planar MOSFETs and post-CMOS-era starting at gate lengths of 6 nm. Introduction: The Driving Forces for Transistor Scaling The 2005 revision of the International Technology Roadmap for Semiconductor Industry [1] is showing a change in technology node introduction from a two-year to a three-year cycle. A stable rate of about 30% of transistor scaling every two years, observed over the last four decades, is about to slow down to about 30% decrease of transistor size every three years. (The technology nodes are, most commonly, specified by the minimum half-pitch of first metal interconnect.) This is not the first time that the technology roadmap predicts a slow down in transistor scaling: the very first edition of ITRS (TRS in 1994) prognosticated that the technology nodes beyond half-micron, i.e. starting with 0.35μm, will require three years to be developed and deployed. The past decade appears to teach that such forecasts have been received by the industry as targets to be exceeded. The 90 nm node went into production in 2003, 65 nm node is being currently introduced into production, and 45 nm technology is expected – as per ITRS roadmap to be in production sometime during 2009-2010. However, many IDMs are striving to achieve this milestone a year or more earlier than forecasted by ITRS. Many of the front-end and back-end process challenges relate to the realization that continued CMOS scaling will require the introduction of new materials, new processes, and new transistor architectures in order to perpetuate Moore’s Law [2] for the foreseeable future. Various responses to the crucial challenge of CMOS scaling seek to reconcile the conflicting requirements of reducing the transistor area, reducing the dynamic power, and reducing off-state power consumption, while increasing the circuit performance. At the present point in time, continued transistor scaling is causing currently used front-end materials to approach their fundamental physical limits. The most prominent example is the disappearing gate silicon dioxide approaching a physical thickness of two atomic layers. The limited ability of photolithography to produce small features in photoresist compounds further the scaling predicament. End of Conventional Scaling and Forces Driving the MOSFET Development When mulling possible alternatives to the planar MOSFET, it is instructive to take a closer look at the forces driving future CMOS technology development. For leading-edge logic chips, the ITRS road map updated in 2005 [1] postulates continued rapid scaling in the physical gate length and other transistor dimensions. Scaling allows to squeeze more transistors into the same space and realize new or more functionalities. Fig.1 shows the ITRS view on the historical overall trend of doubling of transistor count per microprocessor every 18-24 months heading toward 1 billion transistors in a cutting edge microprocessor in 2007. Smaller footprint of a chip results in a higher yield. With scaling it is possible to produce chips with more transistors within a given cost and power consumption window. Thus, besides performance, yield related to the smaller footprint of the circuit is, obviously, a major economic driving force in its own right, and has to be ECS Transactions, 3 (6) 3-17 (2006) 10.1149/1.2357050, copyright The Electrochemical Society

Atomistic study of Metal/High-K interface

This paper describes our ab initio method to evaluate the effective work function of a MOS metal gate on HfO2 oxide which is different from the vacuum one because of the Fermi pinning. The computation relies on Density Functional Theory (DFT) and Many Body theory. Firstly a monoclinic cell is computed using DFT to obtain a band structure; this one is corrected using the GW approximation. Then a stack made of W + HfO2 is computed and using Van de Walle and Martins method, the energy bands alignment along the stack is obtained. Finally HfO2 energies in the stack are corrected according to our previous computation on the HfO2 cell. This calculation brings an evaluation of the valence band offset at the W/HfO2 interface and the effective work function of W on HfO2.