David M. Dobuzinsky

Reaction mechanisms of plasma- and thermal-assisted chemical vapor deposition of tetraethylorthosilicate oxide films

Plasma- and thermal-assisted chemical vapor deposited (CVD) tetrathylorthosilicate (TEOS) oxide films were deposited on silicon substrates using a single-wafer reactor. The deposition kinetics of both plasma and thermal CVD processes were studied as a function of temperature. Film properties and bonding structure were analyzed for as-deposited and annealed films using Fourier transform infrared spectroscopy (FTIR), Auger, x-ray photoelectron spectroscopy (XPS), and nuclear reaction analysis (NRA) techniques. The thermal TEOS films were found to be more porous and to contain more hydrogen, but were more conformal than plasma-deposited TEOS films. Without a plasma, thermal temperatures can assist gas-phase reactions between ozone and TEOS (oxidation) to form conformal oxide films at as low as 200°C. With a plasma, both gas-phase and subsequent surface CVD reactions between TEOS, ozone, and oxygen are substantially enhanced, thus result in CVD films with higher quality

CVD of fluorosilicate glass for ULSI applications

Abstract Interlayer dielectrics are key materials for size reduction and speed enhancement of ultra large scale integrated devices. As intralevel metal spacing is reduced and lower capacitance is required, the choices for inorganic dielectrics are limited, Fluorosilicate glass is a material that is being considered to meet these requirements because it has shown the ability to extend SiO 2 chemical vapor deposition processing. Fluorine addition in a conventional glass improves gap fill while simultaneously lowering the dielectric constant. This paper will review the progress of fluorosilicate glass processing, examine the reliability of these materials, and discuss the role of fluorine in increasing gap fill and lowering the dielectric constant of standard SiO 2 films.

Gate Length and Performance Scaling of Undoped-Body Extremely Thin SOI MOSFETs

In this letter, we show that undoped-body extremely thin SOI (ETSOI) MOSFETs with SOI thickness in the 4-6-nm range have excellent short-channel control down to 20-25-nm gate lengths, suitable for the 22-nm technology node and beyond. We demonstrate that 6-nm-thin ETSOI devices can deliver high drive currents required for logic applications. Finally, we bring to fore the need for improvements in etch and doping processes to reduce series resistance of 4-nm-thin ETSOI devices in order to make them a viable option for the 15-nm technology node.

New leakage mechanism in sub‐5‐nm oxynitride dielectrics

Conduction current in thin (3.5–6.5 nm) oxynitride dielectrics prepared by rapid thermal annealing of SiO2 films in NH3 ambient at high temperature (1100 °C) is studied. Significantly high leakage currents at low fields and independent of temperatures has been observed in films with thickness of 4.5 nm or less. The enhanced conduction is proposed to be direct tunneling current via electron traps located in the dielectric film. This new leakage mechanism in sub‐5‐nm oxynitride dielectric is different from the thicker (5.5 nm or higher) films where the conduction is only slightly enhanced and is temperature dependent. This leakage mechanism could open new applications where significant tunneling current are needed for thicker (<5 nm) films.

New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices

This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.

Evidence of a shallow junction formation from plasma enhanced chemical vapor deposition of boron nitride and silicon boron nitride

Dielectric constant characterization of plasma‐enhanced chemical vapor deposition (PECVD) of boron nitride (BN) and silicon boron nitride (SiBN) films is studied using metal‐insulator‐semiconductor (MIS) and metal‐insulator‐metal (MIM) structures. Using the measurement technique of calculating the dielectric constant value from the capacitance, the average dielectric constant value for the BN and SiBN films deposited under similar conditions can vary as much as 40% (from 2.8 to 4.4). Low dielectric constant values are normally observed on MIS structures where the silicon substrate is n‐type. Detailed C‐V analysis at various test frequencies (100 Hz–1 MHz) shows that the flatband and the threshold voltages shift more than 30 V in n‐type and p‐type substrate wafers, respectively. These C‐V characteristics suggest the formation of a junction at the insulator‐substrate interface. This interface junction is probably formed by the boron‐rich nitride deposition during the transient period and subsequent boron di...

Aluminum dual damascene metallization for 0.175 mm DRAM generations and beyond (invited).

This paper presents an overview of issues associated with Al dual damascene process technology. Different integration schemes are discussed and characteristics of metal fill, planarization and reliability are highlighted. Finally, a comparison is made between Al dual damascene, Al RIE, and Cu dual damascene.

High Selectivity Magnetically Enhanced Reactive Ion Etching of Boron Nitride Films

Oxygen and tetrafluorocarbon magnetically enhanced reactive ion etching (MERIE) of plasma chemical vapor deposited (CVD) boron nitride (BN) and silicon boron nitride (SiBN) was studied for both blanket and submicron patterned films. The relative etch selectivities of the BN and SiBN to oxide (SiO 2 ) and nitride (SiN) were determined. In general, oxygen-rich O 2 /CF 4 MERIE produce very high etch selectivity results while maintaining vertical etch profiles. This etch process expands the potential for use of BN/SiBN in fabrication of subhalf micron devices

Topography induced defocus with a scanning exposure system

Our case study experimentally gauges the defocus component induced by a step in the exposure field substrate, with the edge of the step aligned parallel to the scanning slit. Such steps frequently occur at the border of different chiplets or process monitors within one exposure field. A common assumption is that a step-and-scan imaging system can correct for the majority of such topography, since the wafer is dynamically leveled under the static image plane as it is scanned. Our results show that the range of defocus approaches about 85% of the actual step height and thus contributes significantly to the overall focusing variance. This area on the wafer in which defocus can be observed extends by more than 3mm to both sides of the step. In the same area a degradation of imaging fidelity can be observed in the form of exaggerated proximity effects.

Selection of attenuated phase shift mask compatible contact hole resists for KrF optical lithography

Multiple contact hole resist samples from a variety of DUV resist suppliers, including both acetal and ESCAP chemistries are evaluated on an organic anti-reflective under layer (ARC) using an attenuated phase shift mask (APSM). One sample exhibited excellent surface inhibition and superior lithographic performance for patterning contact holes of 0.2 micrometers imaging size. For most of resists, the process windows are limited by unwanted sidelobe printing through focus. The sensitivity of sidelobe printing to focus can be attributed to lens aberrations. For the first time, we prose to use Depth-of-focus (DOF) loss PWLdof and Exposure latitude (EL) loss PWLel to characterize resists surface inhibition, as well discovered that DOF loss is a sensitive measure of surface inhibition. Similar lithographic performance is obtained from acetal and ESCAP based materials. The two ESCAP resists EB3 and EA2 have better oxide etch resistance than the acetal resist AC1. The top surface reticulation is observed on ESCAP resist EB3 and EA2 during the oxide etch, but not on the acetal resist AC1. 110 nm underexposed resolutions achieved with the resist EA4 at a mask size of 250 nm. Faster resists generally exhibit better resolution but have smaller process windows when side lobe printing is included as a criterion. Selection of a resist formulation for attenuated phase shift applications has to face a compromise between resolution, photospeed, process window and surface inhibition. Finally, ARC operational modes and optical properties had little effect on sidelobe printing, and optimization of PEB temperature is important in suppressing sidelobe printing.