James P. Eckhardt

The clock distribution of the POWER4 microprocessor

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.

Circuit design techniques for the high-performance CMOS IBM S/390 parallel enterprise server G4 microprocessor

This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approaches reduced risk and shortened the design time. The use of timing-driven synthesis/placement methodologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits facilitated the balancing of design time and performance return. The use of robust PLL design, floorplanning, and clock distribution minimized clock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innovations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.

IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology

The IBM eServer z900 microprocessor is a seventh-generation zSeries™ (formerly S/390®) CMOS design which has achieved 1.3-GHz operation. This paper describes the 0.18-µm bulk CMOS, seven-level copper metal process and the high-frequency circuit, integration, and design methodologies developed to achieve this operation. The microprocessor was floorplanned to closely mimic the flow of the microarchitecture pipeline and reduce the communication delay overhead between units. Novel circuit techniques were used in the implementation of the arrays and cache hit detection logic to save power and reduce circuit complexity without sacrificing performance. A four-dimensional gate library and novel synthesis algorithms were developed to yield synthesized control implementations with the performance characteristics of a fully custom circuit design.

Improved performance of IBM Enterprise System/9000 bipolar logic chips

The performance required for logic gate arrays by the IBM Enterprise System/9000TM (ES/9000TM) family of water-cooled processors was obtained by redesigning chips that previously consisted of emitter-coupled logic (ECL) circuits. Multiple bipolar logic circuit families were implemented for the first time on a single IBM chip by using a modular cell approach. In 60% of the ECL circuits, ac coupling in ECL gates reduced the maximum operating power per ECL circuit on ES/9000 chips by S0% and decreased the signal delay per loaded gate by 30%, to 150 ps. About 10-20% of the remaining ECL circuits were replaced by differential current switches (DCS) which dissipated less power and improved the overall chip performance. Circuits to communicate between ECL and DCS circuit families and to improve DCS circuit reliability were included on the ES/9000 chips without affecting logic function density. Introduction Recent advances in bipolar logic semiconductor processing have increased circuit densities on a cliip by an order of magnitude [1, 2]. However, packaging improvements have only doubled the quantity of heat that can be removed from a chip [3]. Consequently, a 50% reduction in the average operating power per logic circuit is required. Bipolar chips in IBM 3090TM processors are composed of ECL circuits which operate at high (15 mW/single phase) power and dissipate significant quantities of heat. In ES/9000 chips, a decrease in power per circuit increases the delays due to the load associated with the capacitance of interconnecting wires. The interconnections introduce a measure of circuit loading which doubles the sensitivity of a circuits performance to fan-out and wire lengths. Vertical geometry device design improvements reduce delays with intrinsic, but not extrinsic, loads. Advanced metallurgies do not compensate for the high wiring capacitance that arises from the longer wire lengths due to a doubling of the ES/9000 chip areas. The performance of gate arrays required by the ES/9000 family of mainframe

An advanced optical diagnostic technique of IBM z990 eServer microprocessor

In this paper, we describe an advanced optical diagnostic technique used for diagnosing the IBM z990 eServer microprocessor (Slegel et al., 2004). Time-to-market pressure demands quick diagnostic turnaround time and high diagnostic resolution while the ever increasing design complexity, density, cycle time, and shrinking technologies dramatically add difficulties to diagnostics. Although design-for-test (DFT) and design-for-diagnostics (DFD) features are implemented in the latest microprocessors to help easing the diagnostic efforts, they may still not be sufficient to diagnose certain fails. The well-known picosecond imaging circuit analysis (PICA) (Kash and Tsang, 1997) tool, equipped with the high quantum efficiency superconducting single-photon detector (SSPD,) shows a unique diagnostic capability for optically probing the internal nodes of a chip. Several hard-to-diagnose examples will be used to demonstrate the unique capabilities of this technique

High performance packaged electronics for the IBM ES9000 mainframe

An 1100 circuit bipolar gate array and a multi-chip high density glass-ceramic module are described. The chip features multiple logic circuit families built using a modular cell approach. Key features include use of a capacitor for faster ECL delays and the introduction of a 200 mV signal swing differential cascode current switch. The module offers a glass ceramic substrate featuring a dielectric constant of 5.2 and a total of 63 layers of metallization. The cooling capability has been increased to 30 W per chip.<<ETX>>

A SOI specific PLL for 1 GHz microprocessors in 0.25 /spl mu/m 1.8 V CMOS

A phase-locked loop (PLL) in silicon over insulator (SOI) for clock generation for CMOS processors can be used on all chips in a mainframe nest which constitute up to a 10-way computer. Test site measurements show a continuous range of operation between 65 MHz and 1.3 GHz with 12 ps steady-state jitter.