Alan J. Weger

Thermal-aware task scheduling at the system software level

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System(OS) and existing hardware support.

Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements

An experimental technique is presented, which allows for spatially-resolved imaging of microprocessor power (SIMP). In a first step this method utilizes infrared (IR) thermal imaging, while the processor is effectively cooled using an IR-transparent heat sink. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running full workloads. In this paper we have applied the SIMP method to the dual core PowerPCtrade970MP microprocessor to measure detailed temperature and power distributions under full operating conditions. In the first part of the paper the impact of power and temperature limitations of high performance CMOS chips is discussed in detail, where we distinguish between hotspot-limited (or temperature-limited) and power-limited chips. The discussion shows the importance of temperature and power distributions for chip floor planning, layout, design and architecture. Second, we present the experimental details of the SIMP method, which is applied to the dual core PowerPC970MP to directly measure the temperature and power fields as a function of workload and frequency. A pronounced movement of the hotspot location is observed. Finally, the hotspot of a competitive microprocessor is compared by measuring temperature efficiencies (temperature increase/performance) for the same workloads and cooling conditions

A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2

A switched-capacitor DC-DC voltage converter in 45nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm2 for 2V-to-0.95V conversion at 100MHz. Operation in step-up and step-down modes is demonstrated. Combined with stacked voltage domains, self-regulation capability enables further efficiency improvement.

The clock distribution of the POWER4 microprocessor

The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.

Spatially-resolved imaging of microprocessor power (SIMP): hotspots in microprocessors

In this paper we present the details of a new technique, which allows for spatially-resolved imaging of microprocessor power (SIMP) under full operational conditions. The method involves two steps: In the first step it utilizes infra-red (IR) thermal imaging, while an IR-transparent coolant flows through a specially designed cooling cell directly over the microprocessor. In the second step the underlying power distribution is derived by determining the temperature fields for each individual power source on the chip. The measured chip temperature distribution is then represented as a superposition of these temperature fields. The SIMP data reveals significant temporal and spatial variations of the microprocessor power/temperature distribution, which can be attributed to the circuit layout as well as to the varying utilization levels across the processor while running real workloads. More specifically, strong non-uniformities or hotspots in the microprocessor power distributions are observed, which have significant implications for packaging and cooling designs

Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBMs 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup

This paper will demonstrate the synthesis of the high current pulse source method (e.g. used in transmission line pulse (TLP) systems) and the Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the evolution of ESD and latchup can be evaluated in semiconductor devices, and in peripheral circuits at a wafer level or product level. The methodology described in this publication allows for visualization of ESD and latchup, events (e.g. animation in a picosecond time regime). The synthesis of the transmission line pulse (TLP) method and the PICA method allows for the extension of the ESD TLP methodology to terminal currents and spatial and time domain analysis for electrical characterization and reliability analysis, and the high current pulsed source extends the utilization of the PICA methodology for failure analysis on wafer and chip levels.

MARVEL — Malicious alteration recognition and verification by emission of light

This paper presents a new technique for detecting chip alterations using intrinsic light emission in combination with electrical test. The key idea of this method is based on the fact that any active device emits infrared light emission when it is powered on. High sensitivity photon detectors can be employed to capture the weak emission while the chip under test is powered on and electric stimuli are applied to it. In particular, two main families of electrical test modes, static and dynamic, can be applied. Positive results of the application of this methodology as well as key challenges will be discussed in the paper, including spatial resolution, imaging processing, data interpretation, etc.

Photon emission microscopy of inter/intra chip device performance variations

We propose a simple, noninvasive, optical technique to measure intra-wafer and intra-chip MOSFET performance variations. Technique utilizes correlation between device performance and weak near-infrared emission from its off-state current. It maps performance variations, producing quantitative data. We experimentally demonstrate our technique on 130 nm SOI microprocessor.

Power management of multi-core chips: challenges and pitfalls

Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, we examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that we pose is: How to ensure that such managed systems are “energy-secure” and how to pursue pre-silicon modeling to ensure such security? In other words, we address the robustness and security issues of such systems. We discuss new advances in energy-secure power management, starting with an assessment of potential vulnerabilities in systems that do not address such issues up front.