Jan Höntschel

Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p-metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n-MOSFET is embedded silicon-carbon (eSi:C). However, n-MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.

Improving accuracy and precision of strain analysis by energy-filtered nanobeam electron diffraction.

This article deals with uncertainty in the analysis of strain in silicon nanoscale structures and devices using nanobeam electron diffraction (NBED). Specimen and instrument related errors and instabilities and their effects on NBED analysis are addressed using a nanopatterned ultrathin strained silicon layer directly on oxide as a model system. We demonstrate that zero-loss filtering significantly improves the NBED precision by decreasing the diffuse background in the diffraction patterns. To minimize the systematic deviations the acquired data were verified through a reliability test and then calibrated. Furthermore, the effect of strain relaxation by specimen preparation using a FIB is estimated by comparing profiles, which were acquired by analyzing slices of strained structures in a 220-nm-thick region of the sample (invasive preparation) and the entire strained nanostructures, which are embedded in a thicker region of the same sample (noninvasive preparation). Together with the random deviation, the corresponding systematic shift results in a total deviation of ∼1 × 10(-3) for NBED analyses, which is employed to estimate the measurement uncertainty in the thinner sample region. In contrast, the strain in the thick sample region is not affected by the preparation; the systematic shift reduces to a minimum, which improves the total deviation by ∼50%.

Suppression of the corner effects in a 22 nm hybrid Tri-Gate/planar process

A hybrid Tri-Gate/planar process was investigated by 3-D process and device simulations. Electrostatics of a Tri-Gate and a planar transistor sharing the same well, halo, and S/D have been compared. The suppression of the Tri-Gate corner effect was studied by corner implantation and additional corner rounding after Tri-Gate fin formation. Corner implantation is useful for retargeting Tri-Gate threshold voltage independent of shared planar implantation settings. Corner rounding allows a reduction of electric field overlap, suppressing corner leakage path and improve ION-IOFF performance.

Effect of source/drain-extension dopant species on device performance of embedded SiGe strained p-metal oxide semiconductor field effect transistors using millisecond annealing

This article shows the importance of source/drain extension dopant species on the performance of embedded silicon-germanium strained silicon on insulator p-metal oxide semiconductor field effect transistor (MOSFET) devices, in which the activation was done using only high temperature ultrafast annealing technologies. BF2 and boron were investigated as source/drain extension dopant species. In contrast to unstrained silicon p-MOSFETs, boron source/drain extension implantations enhance device performance significantly compared to devices with BF2 source/drain extension implantations. Measurements show a 30% mobility enhancement and lower external resistance for the devices with boron source/drain extension implantations. The reason for this lies in the amorphization nature of BF2 implantations. Remaining defects after implant annealing affect the stress transfer from the embedded silicon-germanium and the overall hole mobility which leads to the observed performance degradation. Furthermore, TCAD simulation...

Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process

For future scaling to the end of the ITRS roadmap, novel structures like FinFETs are required to improve electrostatic integrity of MOSFETs with gate lengths shorter than 35 nm [1–4]. Classic fully-depleted FinFETs with a high aspect ratio are not compatible with existing planar process flows. A Tri-Gate transistor has the advantage of being more compatible. It is even possible to produce low-profile Tri-Gates in parallel to planar MOSFETs [5], with shared Tri-Gate and planar implants and common-use of source/drain epi and dual band-edge metal gate workfunctions. This maintains the design flow, saves mask count, allows reuse of analog and high-voltage I/O designs, while exploiting Tri-Gates in high speed logic and low minimum voltage.

Simulation and optimization of Tri-Gates in a 22 nm hybrid Tri-Gate/planar process

A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows a substantial improvement of subthreshold slope, DIBL, and VT-rolloff for Tri-Gates. The electrical behavior of the Tri-Gate transistor has been studied for various Tri-Gate heights and widths. A large space of Tri-Gate dimensions outperformed planar in terms of electrostatics and ION-IOFF characteristics.

Mobility and strain effects for and oriented silicon and SiGe transistor channels

The impact of compressive and tensile stress on CMOS performance is studied for <;100>; and <;110>; oriented silicon and SiGe channels. The <;110>; channel direction is found to be more stress sensitive whereas the <;100>; oriented transistor has a higher initial hole mobility. These results recommend to use the <;110>; channel orientation for high performance application due to the high drive current gain and <;100>; channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.

Simulation of asymmetric doped high performance silicon on insulator metal oxide semiconductor field effect transistors for very large scale integrated complementary metal oxide semiconductor technologies

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

Design and Optimization of Vertical CEO‐T‐FETs with Atomically Precise Ultrashort Gates by Simulation with Quantum Transport Models

The cleaved‐edge overgrowth (CEO) technique offers an innovative approach to designing novel quantum sized field‐effect transistors (FETs) with a T‐like gate‐to‐channel structure. Numerical simulations of vertical CEO‐T‐FETs have been carried out to optimize the structure and predict device performance. For the simulation the 2D/3D device simulator SIMBA is used, which is capable of dealing with complex device geometries as well as with several physical models represented by certain sets of partial differential equations.