Ralf Illgen

Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.

Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p-metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n-MOSFET is embedded silicon-carbon (eSi:C). However, n-MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.

Suppression of the corner effects in a 22 nm hybrid Tri-Gate/planar process

A hybrid Tri-Gate/planar process was investigated by 3-D process and device simulations. Electrostatics of a Tri-Gate and a planar transistor sharing the same well, halo, and S/D have been compared. The suppression of the Tri-Gate corner effect was studied by corner implantation and additional corner rounding after Tri-Gate fin formation. Corner implantation is useful for retargeting Tri-Gate threshold voltage independent of shared planar implantation settings. Corner rounding allows a reduction of electric field overlap, suppressing corner leakage path and improve ION-IOFF performance.

Effect of source/drain-extension dopant species on device performance of embedded SiGe strained p-metal oxide semiconductor field effect transistors using millisecond annealing

This article shows the importance of source/drain extension dopant species on the performance of embedded silicon-germanium strained silicon on insulator p-metal oxide semiconductor field effect transistor (MOSFET) devices, in which the activation was done using only high temperature ultrafast annealing technologies. BF2 and boron were investigated as source/drain extension dopant species. In contrast to unstrained silicon p-MOSFETs, boron source/drain extension implantations enhance device performance significantly compared to devices with BF2 source/drain extension implantations. Measurements show a 30% mobility enhancement and lower external resistance for the devices with boron source/drain extension implantations. The reason for this lies in the amorphization nature of BF2 implantations. Remaining defects after implant annealing affect the stress transfer from the embedded silicon-germanium and the overall hole mobility which leads to the observed performance degradation. Furthermore, TCAD simulation...

Study of 22/20nm Tri-Gate transistors compatible in a low-cost hybrid FinFET/planar CMOS process

For future scaling to the end of the ITRS roadmap, novel structures like FinFETs are required to improve electrostatic integrity of MOSFETs with gate lengths shorter than 35 nm [1–4]. Classic fully-depleted FinFETs with a high aspect ratio are not compatible with existing planar process flows. A Tri-Gate transistor has the advantage of being more compatible. It is even possible to produce low-profile Tri-Gates in parallel to planar MOSFETs [5], with shared Tri-Gate and planar implants and common-use of source/drain epi and dual band-edge metal gate workfunctions. This maintains the design flow, saves mask count, allows reuse of analog and high-voltage I/O designs, while exploiting Tri-Gates in high speed logic and low minimum voltage.

Simulation and optimization of Tri-Gates in a 22 nm hybrid Tri-Gate/planar process

A Tri-Gate structure built into a planar 22 nm bulk process was investigated by 3-D device simulations (Sentaurus D-2010). The planar process flow sequence was extended with extra Tri-Gate patterning, but otherwise all implants were shared, as could be done in simultaneous processing of planar and Tri-Gate CMOS. A comparison of planar and Tri-Gate transistors with the same planar dopant profiles shows a substantial improvement of subthreshold slope, DIBL, and VT-rolloff for Tri-Gates. The electrical behavior of the Tri-Gate transistor has been studied for various Tri-Gate heights and widths. A large space of Tri-Gate dimensions outperformed planar in terms of electrostatics and ION-IOFF characteristics.

Strained isolation oxide as novel overall stress element for Tri-Gate transistors of 22nm CMOS and beyond

This 3-D TCAD study demonstrates a new stress element by strained isolation oxide for Tri-Gate and similar FinFET structures. The simulation shows an uniform improvement of N- and PMOS drive current (10 %) by using a tensile strained isolation material between the fins processed on standard (100) bulk wafer with 110>; channel direction. Therefore it is a simple low-cost stress method for Tri-Gate and FinFET structures of 22nm technologies and beyond. The main stress direction is located along the channel width with a maximum near the pn-junctions. The stress effect can be improved further with reduced gate length which shows the compatibility of strained isolation oxide to future transistor generations.

Line Edge and Gate Interface Roughness Simulations of Advanced VLSI SOI-MOSFETs

The influence of line edge and gate interface roughness on SOI-MOSFET performance is studied by simulation. Both types of roughness were implemented in the device simulator SIMBA through the Fourier synthesis approach and the simulations were performed with the drift diffusion and the quantum drift diffusion models. Scaled transistors showed more sensitivity to rough interfaces with shallow junctions.

RF performance of 28nm PolySiON and HKMG CMOS devices

The impact of scaling in advanced RF/MS-CMOS has been extensively discussed but there has not been a publication that compares the RF characteristics of 28nm high-K metal gate HKMG and PolySiON technologies fabricated in the same facility. In this work, we show that HKMG improves transistor fT and increases varactor tunning range. However, it can actually decrease fmax. We examine how process features made to optimize cost and digital performance impact the RF performance. Process features which improve DC current and gm, including HKMG also give higher fT. However, fmax is sensitive to gate resistance and PolySiON has an advantage here.

Mobility and strain effects for and oriented silicon and SiGe transistor channels

The impact of compressive and tensile stress on CMOS performance is studied for <;100>; and <;110>; oriented silicon and SiGe channels. The <;110>; channel direction is found to be more stress sensitive whereas the <;100>; oriented transistor has a higher initial hole mobility. These results recommend to use the <;110>; channel orientation for high performance application due to the high drive current gain and <;100>; channel orientation for low power applications where no stress elements are included to ease the overall process complexity and to decrease costs.