Stefan Flachowsky

Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.

Doped Hafnium Oxide – An Enabler for Ferroelectric Field Effect Transistors

Ferroelectrics are very interesting materials for nonvolatile data storage due to the fact that they deliver very low power programming operation combined with nonvolatile retention. For 60 years researchers have been inspired by these fascinating possibilities and have tried to build ferroelectric memory devices that can compete with mainstream technologies in their respective time. The progress of the current concepts is limited by the low compatibility of ferroelectrics like PZT with CMOS processing. Therefore, PZT or SBT based 1T1C ferroelectric memories are not scaling below 130 nm and 1T ferroelectric FETs based on the same materials are still struggling with low retention and very thick memory stacks. Hafnium oxide, a standard material in sub 45 nm CMOS, can show ferroelectric hysteresis with promising characteristics. By adding a few percent of silicon and annealing the films in a mechanically confined manner. Boescke et al. demonstrated ferroelectric hysteresis in hafnium oxide for the first time. Recently, a large number of dopants including Y, Al, Gd and Sr have been used to induce ferroelectricity in HfO2. This paper reviews the current status of hafnium oxide based ferroelectrics, its application to field effect transistors and puts this approach into a wider context of earlier developments in the field.

Evidence of single domain switching in hafnium oxide based FeFETs: Enabler for multi-level FeFET memory cells

Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film. Here we report for the first time the evidence of single ferroelectric (FE) domain switching in such scaled devices. These properties are sensed in terms of abrupt threshold voltage (VT) shifts leading to stable intermediate VT levels. We emphasize that this feature enables multi-level cell (MLC) FeFETs and gives a new perspective on steep subthreshold devices based on ferroelectric HfO2.

Switching Kinetics in Nanoscale Hafnium Oxide Based Ferroelectric Field-Effect Transistors

The recent discovery of ferroelectricity in thin hafnium oxide films has led to a resurgence of interest in ferroelectric memory devices. Although both experimental and theoretical studies on this new ferroelectric system have been undertaken, much remains to be unveiled regarding its domain landscape and switching kinetics. Here we demonstrate that the switching of single domains can be directly observed in ultrascaled ferroelectric field effect transistors. Using models of ferroelectric domain nucleation we explain the time, field and temperature dependence of polarization reversal. A simple stochastic model is proposed as well, relating nucleation processes to the observed statistical switching behavior. Our results suggest novel opportunities for hafnium oxide based ferroelectrics in nonvolatile memory devices.

Strained Silicon Devices

Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed.

Detailed simulation study of embedded SiGe and Si:C source/drain stressors in nanoscaled silicon on insulator metal oxide semiconductor field effect transistors

Strained silicon techniques have become an indispensable technology feature, enabling the momentum of semiconductor scaling. Embedded silicon-germanium (eSiGe) is already widely adopted in the industry and delivers outstanding p-metal oxide semiconductor field effect transistor (MOSFET) performance improvements. The counterpart for n-MOSFET is embedded silicon-carbon (eSi:C). However, n-MOSFET performance improvement is much more difficult to achieve with eSi:C due to the challenging process integration. In this study, detailed TCAD simulations are employed to compare the efficiency of eSiGe and eSi:C stressors and to estimate their potential for performance enhancements in future nanoscaled devices with gate lengths down to 20nm. It is found that eSiGe as a stressor is superior to eSi:C in deeply scaled and highly strained devices due to its easier process integration, reduced parasitic resistance, and nonlinear effects in the silicon band structure, favoring hole mobility enhancement at high strain levels.

A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs

We successfully implemented a one-transistor (1T) ferroelectric field effect transistor (FeFET) eNVM into a 28nm gate-first super low power (28SLP) CMOS technology platform using two additional structural masks. The electrical baseline properties remain the same for the FeFET integration and the JTAG-controlled 64 kbit memory shows clearly separated states. High temperature retention up to 250 °C is demonstrated and endurance up to 105 cycles was achieved. The FeFET unique properties make it the best candidate for eNVM solutions in sub-2x technologies for low-cost IoT applications.

Suppression of the corner effects in a 22 nm hybrid Tri-Gate/planar process

A hybrid Tri-Gate/planar process was investigated by 3-D process and device simulations. Electrostatics of a Tri-Gate and a planar transistor sharing the same well, halo, and S/D have been compared. The suppression of the Tri-Gate corner effect was studied by corner implantation and additional corner rounding after Tri-Gate fin formation. Corner implantation is useful for retargeting Tri-Gate threshold voltage independent of shared planar implantation settings. Corner rounding allows a reduction of electric field overlap, suppressing corner leakage path and improve ION-IOFF performance.

Correlation between the macroscopic ferroelectric material properties of Si:HfO2 and the statistics of 28 nm FeFET memory arrays

ABSTRACT With the discovery of ferroelectric hafnium oxide (FE-HfO2), the ferroelectric field effect transistor (FeFET), a long-term contender for non-volatile data storage, has finally managed to scale to the 2× nm technology node. Here for the first time, we correlate the thickness dependent ferroelectric properties of Si:HfO2 with the memory characteristics of small (56 bit) FeFET arrays. First, an electrical and structural analysis of metal-ferroelectric-metal capacitors is given. Even though possessing room-temperature deposited top electrodes, TiN / Si:HfO2 (20 nm) / TiN capacitors are showing deteriorated polarization characteristics as compared to their 10 nm Si:HfO2 counterparts. This could be attributed to an increased monoclinic phase fraction, as indicated by small-signal capacitance voltage and grazing incidence X-ray diffraction measurements. Identical Si:HfO2 thin films with thicknesses of 10 nm and 20 nm respectively, were utilized in a 28 nm high-k metal-gate CMOS flow to form small FeFET memory arrays of AND architecture. After extracting the most suitable operating conditions from erase matrix, single cell evaluation was performed by standard VP/3 program and a novel VP/3 positive-source drain erase scheme. Array cells incorporating 10 nm Si:HfO2 films showed a maximum memory window of 1.03 V whereas cells incorporating 20 nm Si:HfO2 films could reach up to 1.57 V. Moreover, in accordance to the basic material properties, the previously observed increased monoclinic phase fraction in 20 nm Si:HfO2 thin films correlate well with a reduced number of functional FeFET cells.

Effect of source/drain-extension dopant species on device performance of embedded SiGe strained p-metal oxide semiconductor field effect transistors using millisecond annealing

This article shows the importance of source/drain extension dopant species on the performance of embedded silicon-germanium strained silicon on insulator p-metal oxide semiconductor field effect transistor (MOSFET) devices, in which the activation was done using only high temperature ultrafast annealing technologies. BF2 and boron were investigated as source/drain extension dopant species. In contrast to unstrained silicon p-MOSFETs, boron source/drain extension implantations enhance device performance significantly compared to devices with BF2 source/drain extension implantations. Measurements show a 30% mobility enhancement and lower external resistance for the devices with boron source/drain extension implantations. The reason for this lies in the amorphization nature of BF2 implantations. Remaining defects after implant annealing affect the stress transfer from the embedded silicon-germanium and the overall hole mobility which leads to the observed performance degradation. Furthermore, TCAD simulation...