Jan Saijets

Simulation and Modeling of Self-switching Devices

A new type of nanometer scale nonlinear device, called self-switching device (SSD) is realized by tailoring the boundary of a narrow semiconductor channel to break its symmetry. An applied voltage V not only changes the potential profile along the channel direction, but also either widens or narrows the effective channel width depending on the sign of V. This results in a strongly nonlinear I-V characteristic, resembling that of a conventional diode. Because the structure resembles a diode-connected FET (gate and drain shorted), we have modeled the device as a sideways turned FET, so that the trench width t corresponds to insulator thickness tox and conducting layer thickness Z (inside the semiconductor!) corresponds to channel width W.

A Comparative Study of Various MOSFET Models at Radio Frequencies

We have compared and systematically evaluated four mainstream MOSFET models (EKV, SPICE Level 3, Bsim3v3 and Philips MOS Model 9) at radio frequencies. Furthermore, we have tested some improvements proposed for the models in the GHz region. In the first phase complete scalable DC models were determined, and the high frequency model parameters were then extracted from properly designed RF test transistors by using S-parameter fitting and capacitance measurements. The inaccuracies in the AC results were found to be mainly a consequence of the problems in the modelling of the DC conductances. The Bsim3v3 and MOS9 models seem to yield the most realistic AC characteristics of the models. The accuracy of the MOS9 model is slightly inferior to that of the Bsim3v3 model, but it may be improved to the same level or even beyond, simply by adding a gate-bulk zero-bias capacitance to the MOSFET equivalent circuit, which has been done in many commercial circuit simulators. The best models give accurate results up to 4 GHz, and after a careful parameter extraction even at 10 GHz. We also have demonstrated the applicability of the improved models in the design of a LNA CMOS circuit.

MOSFET RF Extraction Uncertainties Due To S Parameter Measurement Errors

The effect of S parameter measurement errors resulting from vector network analyzer uncertainties on RF MOSFET parameter extraction are analyzed. The uncertainty effects on the MOSFET small signal equivalent circuit are studied. The lower uncertainty specifications of a high end network analyzer were used as the basis for the analysis. The results suggest that the input resistance extraction is very inaccurate. Transconductance and feedback capacitance characterization can be extracted with less than 4% error at low frequencies below 2–3GHz. Output capacitance is challenging because it can easily be 50% erroneous. Output resistance can be extracted with less than 20% error for a output real part range of 3Ω to 1kΩ.

Silicon self-switching-device based logic gates operating at room temperature

This paper presents first functional operational results of logic gates based on Silicon nano scale self switching devices (SSDs) and side gated transistors (SGTs). The devices are manufactured with Silicon-on- Insulator (SOU technology and are operative in room temperature. The circuits show correct logic operation. The performance parameters are still short of practical values, but ways of bringing them to acceptable level for real applications are discussed.

Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology

This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz. The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.

Feasibility of a cryogenic SiGe amplifier at 4 k

The feasibility of an integrated SiGe amplifier with 1 GHz band width and 30 dB gain for cryogenic temperatures has been studied. The standard models do not simulate special low temperature phenomena and give erroneous results below 50 K. We have circumvented this problem by using an experimentally defined “effective temperature” in simulations. Thereafter we have studied a cascade amplifier topology with trade-offs between gain, noise figure, band width, area and power consumption.

Influence of Substrate Bias on the Structural and Dielectric Properties of Magnetron-Sputtered BaxSr1-xTiO3 Thin Films

The application of a substrate bias during rf magnetron sputtering alters the crystalline structure, grain morphology, lattice strain and composition of BaxSr1-xTiO3 thin films. As a result, the dielectric properties of Pt/BaxSr1-xTiO3/Pt parallel-plate capacitors change significantly. With increasing substrate bias we observe a clear shift of the ferroelectric to paraelectric phase transition towards higher temperature, an increase of the dielectric permittivity and tunability at room temperature, and a deterioration of the dielectric loss. To a large extent these changes correlate to a gradual increase of the tensile in-plane film strain with substrate bias and an abrupt change in film composition.

AC characteristics of the MOSFET parasitic channel series resistances when absorbed into the current description

The AC behavior of absorbed parasitic series resistances of MOSFET models were compared to the conventional lumped resistance approach both theoretically and with real device values. The result suggested that absorbing the parasitic channel series resistances into the current description decreases the AC accuracy of the MOS model compared to conventional model with lumped resistances. Comparison were made with the input, output and gain and backward gain characteristics and it seems that the largest differences can be seen in the input and output behavior. The simple theoretical study of the two modeling approaches is confirmed by empirical comparisons of an 80 x 1.0 mum x 90 nm NMOS device characteristics up to 110 GHz.