Jan Holmberg

Bandwidth limitations of impedance matched ideal dipoles

Using circuit theory and Chus network representations of the wave impedance of the lowest spherical multipole field, the Ideal dipole, an explicit expression is derived for the upper limit for the impedance bandwidth obtainable for an ideal, lossless, linearly polarized antenna. The expression embodies the network character of an ideal antenna and its role in the guidance of energy between the feed point and the free-space interface, making it more appropriate as a reference than the theoretical radiation quality factor (Q). Moreover, practical antennas do not always manifest a clear single-pole behavior, undermining the basic assumption of a reciprocal relation between Q and the bandwidth.

Marked point process framework for living probabilistic safety assessment and risk follow-up

We construct a model for living probabilistic safety assessment (PSA) by applying the general framework of marked point processes. The framework provides a theoretically rigorous approach for considering risk follow-up of posterior hazards. In risk follow-up, the hazard of core damage is evaluated synthetically at time points in the past, by using some observed events as logged history and combining it with re-evaluated potential hazards. There are several alternatives for doing this, of which we consider three here, calling them initiating event approach, hazard rate approach, and safety system approach. In addition, for a comparison, we consider a core damage hazard arising in risk monitoring. Each of these four definitions draws attention to a particular aspect in risk assessment, and this is reflected in the behaviour of the consequent risk importance measures. Several alternative measures are again considered. The concepts and definitions are illustrated by a numerical example.

60 GHz Frequency Conversion 90 nm CMOS Circuits

This paper presents design and a characterisation of an active single-stage single-ended 30 to 60 GHz frequency doubler and a resistive down conversion mixer with differential buffer stage. These MMICs are realised using 90-nm CMOS process. The doubler exhibit 7.1 dB conversion loss and 10.8 dB fundamental frequency suppression with 0 dBm input power and 13.7 mW power consumption. Maximum output power of -4.2 dBm is achieved with 5 dBm input power. The mixer has 9.8 dB conversion gain with +5 dBm local oscillator level. The compression point P1dB is -2 dBm with 14 mW power consumption.

Risk follow-up by probabilistic safety assessment : experience from a Finnish pilot study

Abstract Risk follow-up by probabilistic safety assessment (PSA) provides a systematic method to analyze incidents. Events can be evaluated from the safety point of view to get feedback from operating experience, for the identification of risk contributors and for the verification of PSA models. This paper is concerned with the risk follow-up methodology, which is based on a marked point process framework. This framework provides a theoretically rigorous method for retrospective risk evaluations. Basic concepts for the modelling and an evaluation of the operating history by PSA are presented, and a Finnish pilot study on risk follow-up is summarized. We recommend the ‘total memory approach’ for the assessment of the unavailability of the standby safety systems. According to our experience, accurate evaluations with time-dependent component models are not necessarily needed but simplifying approximations can be used. The modelling of common cause failures remains a problem in practice, however, because there are not enough data to distinguish them properly.

100 GHz push-push oscillator in 90 nm CMOS technology

A 100 GHz fixed-tuned oscillator was designed and fabricated using a 90 nm bulk CMOS process. Push-push mode was chosen to improve the power output. The oscillator exhibits -3 dBm output power at 101 GHz with 27 mW power consumption. The measured SSB phase noise is -85 dBc/Hz at 1 MHz offset Resonators are implemented with transmission lines to avoid the need of high quality capacitors and inductors.

Two-way vector modulator SiGe MMIC for millimeter-wave phased array applications

This paper presents a two-way vector modulator integrated circuit aimed for millimeter wave phased array systems. The active vector modulator is based on the Cartesian topology. Phase can be tuned continuously 360 degrees and the usable gain control range is more than 10 dB. The chip includes a low-noise preamplifier and a buffer amplifier in both receive and transmit paths, which are coupled together using a T-junction. The chip can be used from 60 to 80 GHz and the maximum gain is 30 dB at 67 GHz and The chip is processed in 0.35μm silicon germanium technology. Size of the chip including the pads is 2.5 × 1 mm2 from which one vector modulator core occupies 0.3 × 0.3 mm2.

Multiband integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm2. The RF front end consists of three parallel signal channels intended for L,C and X-band of the SAR receiver. The baseband (BB) is selectable between 50 MHz and 160 MHz bandwidths through switches. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 dB and 37 dB and noise figure of 11 dB and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz baseband and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz baseband and 8 bit mode ADC.

AC characteristics of the MOSFET parasitic channel series resistances when absorbed into the current description

The AC behavior of absorbed parasitic series resistances of MOSFET models were compared to the conventional lumped resistance approach both theoretically and with real device values. The result suggested that absorbing the parasitic channel series resistances into the current description decreases the AC accuracy of the MOS model compared to conventional model with lumped resistances. Comparison were made with the input, output and gain and backward gain characteristics and it seems that the largest differences can be seen in the input and output behavior. The simple theoretical study of the two modeling approaches is confirmed by empirical comparisons of an 80 x 1.0 mum x 90 nm NMOS device characteristics up to 110 GHz.