Markku Åberg

A Single Clocked Adiabatic Static Logic--A Proposal for Digital Low Power Applications

A modified method to construct adiabatic logic is introduced. Advantages of this circuitry over most of the previous ones is that logic behaves in a static mode. In the present research the applicability of a one-phase power clock was studied. The functionality was guaranteed by having the power source frequency much higher than the logic frequency. The new logic gates do not differ much from any standard CMOS logic gates. The only difference is the use of diodes to form logical ‘1’ and ‘0’ states. The static nature of the introduced logic family makes possible to apply the charge recycling technic to other more complex digital circuits and systems. In measurements 77% power saving was achieved compared to a conventional CMOS logic.

Simulation and Modeling of Self-switching Devices

A new type of nanometer scale nonlinear device, called self-switching device (SSD) is realized by tailoring the boundary of a narrow semiconductor channel to break its symmetry. An applied voltage V not only changes the potential profile along the channel direction, but also either widens or narrows the effective channel width depending on the sign of V. This results in a strongly nonlinear I-V characteristic, resembling that of a conventional diode. Because the structure resembles a diode-connected FET (gate and drain shorted), we have modeled the device as a sideways turned FET, so that the trench width t corresponds to insulator thickness tox and conducting layer thickness Z (inside the semiconductor!) corresponds to channel width W.

A Comparative Study of Various MOSFET Models at Radio Frequencies

We have compared and systematically evaluated four mainstream MOSFET models (EKV, SPICE Level 3, Bsim3v3 and Philips MOS Model 9) at radio frequencies. Furthermore, we have tested some improvements proposed for the models in the GHz region. In the first phase complete scalable DC models were determined, and the high frequency model parameters were then extracted from properly designed RF test transistors by using S-parameter fitting and capacitance measurements. The inaccuracies in the AC results were found to be mainly a consequence of the problems in the modelling of the DC conductances. The Bsim3v3 and MOS9 models seem to yield the most realistic AC characteristics of the models. The accuracy of the MOS9 model is slightly inferior to that of the Bsim3v3 model, but it may be improved to the same level or even beyond, simply by adding a gate-bulk zero-bias capacitance to the MOSFET equivalent circuit, which has been done in many commercial circuit simulators. The best models give accurate results up to 4 GHz, and after a careful parameter extraction even at 10 GHz. We also have demonstrated the applicability of the improved models in the design of a LNA CMOS circuit.

MOSFET RF Extraction Uncertainties Due To S Parameter Measurement Errors

The effect of S parameter measurement errors resulting from vector network analyzer uncertainties on RF MOSFET parameter extraction are analyzed. The uncertainty effects on the MOSFET small signal equivalent circuit are studied. The lower uncertainty specifications of a high end network analyzer were used as the basis for the analysis. The results suggest that the input resistance extraction is very inaccurate. Transconductance and feedback capacitance characterization can be extracted with less than 4% error at low frequencies below 2–3GHz. Output capacitance is challenging because it can easily be 50% erroneous. Output resistance can be extracted with less than 20% error for a output real part range of 3Ω to 1kΩ.

A 10-bit, 1.8-GS/s Time-Interleaved Pipeline ADC

In this paper, a 10-bit, 1.8-GS/s time-interleaved analog-to-digital converter (ADC) is presented. The ADC employs 24 parallel 10-bit pipeline ADCs to reach the conversion rate of 1.8 GS/s. Sampling clocks are generated by a delay-locked loop (DLL), which includes a calibration of timing skew. Offset and gain error are calibrated in order to overcome the effects of device mismatch within a channel ADC. The ADC, implemented with a 0.35-mum BiCMOS, achieves an effective number of bits (ENOB) of 7.19 bits with a 764-MHz input while consuming 3.5 W of power.

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 /spl mu/m CMOS

This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.

Silicon self-switching-device based logic gates operating at room temperature

This paper presents first functional operational results of logic gates based on Silicon nano scale self switching devices (SSDs) and side gated transistors (SGTs). The devices are manufactured with Silicon-on- Insulator (SOU technology and are operative in room temperature. The circuits show correct logic operation. The performance parameters are still short of practical values, but ways of bringing them to acceptable level for real applications are discussed.

Implementation experiments of analog nonvolatile memory with a standard 0.35 μ m CMOS

This paper presents a study upon implementation of a nonvolatile memory with a standard CMOS process. The main emphasis is to obtain an analog, continuous value, EEPROM module. The accuracy, reliability and reproducibility performance of the different memory cells have been investigated. Different types of programming method have been tested and compared EEPROM cells have been processed with two different 0.35 μm CMOS processes and two different process runs. Measurement results show that a reliable, medium accuracy, analog EEPROM can be implemented without any process Modifications.

An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

An 25-muW 1.8V 8-bit 10 kS/s successive approximation (SAR) analog to digital converter (ADC) was designed and fabricated in a 0.18 mum CMOS technology for passive UHF RFID applications. The resistive digital to analog converter (DAC) has no sample and hold block and can operate with low power consumption. The proposed comparator can operate at a low supply voltage. The measured total power consumption is 25 muW at a 10 kS/s conversion rate with a 1.8V single supply voltage.

Feasibility of a cryogenic SiGe amplifier at 4 k

The feasibility of an integrated SiGe amplifier with 1 GHz band width and 30 dB gain for cryogenic temperatures has been studied. The standard models do not simulate special low temperature phenomena and give erroneous results below 50 K. We have circumvented this problem by using an experimentally defined “effective temperature” in simulations. Thereafter we have studied a cascade amplifier topology with trade-offs between gain, noise figure, band width, area and power consumption.