Rik Jos

Design of Varactor-Based Tunable Matching Networks for Dynamic Load Modulation of High Power Amplifiers

In this paper, the design of varactor-based tunable matching networks for dynamic load modulation of high power amplifiers (PAs) is presented. Design guidelines to overcome the common breakdown, and tunability problems of the varactors for high power applications are proposed. Based on the guidelines, using commercially available abrupt junction silicon varactors, a tunable matching network is built and measured. The matching network is then used for load modulation of a 1-GHz 7-W class-E LDMOS PA. Static measurements of the load modulated PA show that the power-added efficiency of the PA is improved by an absolute value of 10% at 10-dB backoff. This promising result proves, for the first time, the feasibility of load modulation techniques for high-power applications in the gigahertz frequency range.

A strong reduction in the density of near-interface traps at the SiO2∕4H‐SiC interface by sodium enhanced oxidation

This paper demonstrates how sodium enhanced oxidation of Si face 4H‐SiC results in removal of near-interface traps at the SiO2∕4H‐SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1–10cm2∕Vs) in Si face 4H‐SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these near-interface traps resulting in high inversion channel mobility of 150cm2∕Vs in such transistors. Sodium is incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during the formation of the SiC∕SiO2 interface.

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.

High-Efficiency RF Pulsewidth Modulation of Class-E Power Amplifiers

A new switch-mode power-amplifier (SMPA) topology particularly suitable for energy efficient amplification of RF pulsewidth modulation (RF-PWM) signals is derived. It is analytically shown that high efficiency can be maintained over a wide power dynamic range if the imaginary part of the Class-E load impedance is varied along with the duty cycle (pulsewidth). Using the theory developed, an explicit design procedure is presented that allows practical realization of the proposed topology from the circuit and component specifications. Following the design procedure, and using in-house (Chalmers University, Göteborg, Sweden) SiC varactor diodes to implement the tunable imaginary load impedance, a 2-GHz 10-W peak output power GaN HEMT circuit demonstrator is realized. RF-PWM input signals for characterization of the prototype power amplifier (PA) is generated with a dedicated 65-nm CMOS modulator. The measurements show that a drain efficiency >; 70% can be obtained over an 6.5-dB dynamic range, which verifies the theory presented and demonstrates the feasibility of the proposed PA topology.

Continuous Class-E Power Amplifier Modes

In this brief, a continuum of novel closed-form solutions is derived for class-E power amplifiers (PAs). It is analytically proven that the class-E zero voltage/zero voltage derivative switching conditions can be satisfied for an arbitrarily selected reactive second harmonic switch impedance (<i>Z</i>₂^S). The higher order harmonic currents are terminated capacitively. The conventional class-E, class- <i>E</i>/<i>F</i>₂, and class-<i>EF</i>₂ modes are thus subsets of the continuum. The arbitrary selection of <i>Z</i>₂^S enables robust waveform engineering for performance optimization in specific applications. Furthermore, the theoretical derivation provides important possibilities for wideband class-E PA synthesis.

Characterization of switched mode LDMOS and GaN power amplifiers for optimal use in polar transmitter architectures

In this paper, switched mode power amplifiers classes of operation and device technologies are characterized versus input power and output supply voltage. The results are used to identify optimal control schemes for use in polar transmitter architectures. Then the effects of different control schemes on the requirements for the power amplifier, and the envelope amplifier, as the main building blocks of this architecture, are investigated.

Comparison between oxidation processes used to obtain the high inversion channel mobility in 4H-SiC MOSFETs

In this work two oxidation methods aimed at improving the silicon face 4H-SiC/SiO2 interface are compared. One is an oxidation in N2O performed in a quartz tube using quartz sample holders and the other is a dry oxidation performed in an alumina tube using alumina sample holders. In n-type metal oxide semiconductor (MOS) capacitors the interface state density near the SiC conduction band edge is estimated using capacitance–voltage (C–V) and thermal dielectric relaxation current (TDRC) measurements. N-channel metal oxide semiconductor field effect transistors (MOSFETs) are characterized by current–voltage (I–V) techniques and the inversion channel mobility is extracted. It is shown that the high inversion channel mobility (154 cm2 V−1 s−1) seen in samples oxidized using alumina correlates with a low interface trap density (3.6 × 1011 cm−2). In the case of N2O oxidation the mobility is lower (24 cm2 V−1 s−1) and the interface trap density is higher (1.6 × 1012 cm−2). Room temperature C–V measurements are of limited use when studying traps near the conduction band edge in MOS structures while the TDRC measurement technique gives a better estimate of their density.

SiC Varactors for Dynamic Load Modulation of High Power Amplifiers

SiC Schottky diode varactors with a high breakdown voltage, a high tuning ratio, and a low series resistance have been designed and fabricated. These characteristics are particularly necessary for the dynamic load modulation of high power amplifiers (PAs), which is an attractive alternative to other efficiency enhancement techniques. For a SiC Schottky diode varactor with a 50- radius fabricated by using a graded doping profile, a breakdown voltage of 40 V, a tuning range of 5.6, and a series resistance of 0.9 were achieved. The results show the great potential of this type of varactors for the use in the dynamic load modulation of high power amplifiers.

A Load Modulated High Efficiency Power Amplifier

A load modulation technique based on a high efficiency inverse class-F power amplifier (PA) has been developed at 1 GHz. The active device is an LDMOS transistor. The PA provides a drain efficiency greater than 60 % over a 5 dB output power range with a maximum output power of 41.6 dBm

Sodium Enhanced Oxidation of Si-Face 4H-SiC: A Method to Remove Near Interface Traps

We demonstrate how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2/4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1-10 cm2/Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these nearinterface traps resulting in high inversion channel mobility of 150 cm2/Vs in such transistors. Sodium can be incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during formation of the SiC/SiO2 interface.