Jason F. Ross

Soft Error Sensitivities in 90 nm Bulk CMOS SRAMs

Enhanced single event upset (SEU) sensitivity to low energy protons, as much as 5-6 orders of ten, has been observed in 90 nm epitaxial-bulk complementary metal oxide semiconductor (CMOS) static random access memories (SRAM). Enhancements to process and cell design are discussed.

A Radiation Hardened 16-Mb SRAM for Space Applications

A new high density, high performance 16-Mb static random access memory (SRAM) is being developed in a 0.15 mum CMOS RH15 technology for use in space and other strategic radiation hardened applications. The SRAM design is implemented in a 1.5 Volt, 0.15 micron and seven-layer metal CMOS technology. Using integrated process features and advanced design techniques, a small cell size of 9.3 mum2 was utilized while achieving a SEU radiation hardness of less than IE-12 upsets/bit-day and a worst-case chip performance of less than 15 ns access time.

Incremental Enhancement of SEU Hardened 90 nm CMOS Memory Cell

SEU enhancements were introduced into a radiation hardened 90 nm CMOS technology to achieve upset immunity. An incremental enhancement approach that enables various SEU/performance trade-off was demonstrated on the same basic SRAM cell to achieve various degrees of hardness, by the selective utilization of enhancement features. Single event upset testing, as well as MRED simulation, have demonstrated a significant enhancements achieved with a minimal performance penalty.

The Path and Challenges to 90-nm Radiation-Hardened Technology

Radiation effects analysis on a commercial 90-nm CMOS process has been performed to evaluate hardness potential from a process and design perspective, and to identify techniques to promote radiation hardness enhancement towards achieving suitability for low power space applications.

On-board networks with radiation-hardened 45nm SOI standard components

This paper describes the key components for implementing a modern network for intra-satellite communications at the backplane and spacecraft local area network (LAN) levels. The objective network is capable of supporting orders of magnitude more on-board processing than current architectures based on parallel PCI-bus, MIL-STD-1553B and SpaceWire alone. The RADNET™ family supports the emerging SpaceVPX standard at the backplane level including RapidIO data plane, SpaceWire control plane, and I2C utility plane. RapidIO, SpaceWire and MIL-STD- 1553B are the primary interfaces supported at the spacecraft local area network (LAN) level. Heritage network components are available to support parallel PCI-bus, SpaceWire and MIL-STD-1553B. The latest RADNET components use BAE Systems RH45™ radiation-hardened by design (RHBD) 45nm silicon-on-insulator (SOI) ASIC library and are manufactured at the IBM Trusted foundry. These include a RapidIO network endpoint, an 18-port, 192-Gb/s RapidIO packet switch, and a 16-by-16-lane, 5-Gbaud per lane physical layer serializer-deserializer (SerDes) crosspoint switch. Network architecture, technical challenges, component architectures, development methodology, implementation, programming and path to flight are discussed.

Quad-core radiation-hardened system-on-chip power architecture processor

Based on the QorIQ® system-on-chip processor architecture from Freescale Semiconductor with additional unique features for space applications, the RAD55xxTM system-on-chip platform integrated circuit can be personalized into multiple processor solutions. The RAD55xx platform includes four 32/64 bit Power Architecture® processor cores, three levels of on-die cache memory, dual interleaved DDR3 DRAM controllers, data path acceleration architecture (DPAA) on-die hardware accelerators, a NAND Flash controller, and high I/O throughput based on serializer/deserializer high speed links. Manufactured at the IBM trusted foundry in 45nm silicon-on-insulator (SOI) process technology with copper interconnect and leveraging the radiation-hardened by design RH45TM technology, the RAD55xx platform optimizes power/performance to deliver processor throughput of up to 5.6 GOPS/3.7 GFLOPS, memory bandwidth of up to 102 Gb/s, and I/O throughput of up to 64 Gb/s. Each of the highly efficient RAD5500™ 64-bit cores offers direct addressability to 64 GB of memory, improves double precision floating point performance, and achieves 3.0 Dhrystone MIPS/MHz. The RAD55xx platform is designed for insertion into systems using the SpaceVPX standard, supporting the RapidIO data plane, SpaceWire control plane, and I2C utility plane. Architectural trades, the development methodology, technical challenges, and single board computer solutions are discussed.

Single Event Gate Rupture Testing on 90 nm Bulk CMOS Deep Trench Oxide Capacitors

Single event gate rupture (SEGR) testing on a deep trench oxide capacitor used for the reduction of single event upsets (SEU) in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology indicates that SEGR was not detected.

90-nm Digital Single Event Transient Pulsewidth Measurements

Single event transient (SET) pulsewidth measurements were made on 9SF 90 nm shift registers built with temporal delay latches on epitaxial substrates. Data was gathered using heavy ions from LETs of 9.75 to 58.78 (MeV-cm2)/mg.

Physical Evidence Supporting the Electrical Signature of SEGR on Thin Vertical Oxides

Analysis techniques on a 90 nm deep trench capacitor have provided the physical evidence for a heavy ion induced single event gate rupture (SEGR). The trench capacitor is from a 90 nm bulk complementary metal oxide semiconductor technology and is used for the reduction of single event upsets. SEGR damaged trench oxides are identified via a voltage contrast technique using a focused ion beam. The focused ion beam was used to delayer and expose the deep trenches. A wet chemical etch was used to identify the location of the SEGR leakage path. The oxide rupture location was observed at the top of the deep trench capacitor.

State and Angular Dependence of Single-Event Upsets in an Asymmetric RC-Hardened SRAM Using Deep Trench Capacitors

A marked state dependence and significant reduction in SEU cross section with even small increases in incident angle are reported in an asymmetric RC-hardened 90 nm CMOS SRAM. The effects are attributable to the bias dependence and high aspect ratio of the deep trench capacitor sidewall depletion region, exacerbated by process-induced boron depletion. The asymmetric implementation, using capacitive hardening in only one leg of the SRAM cell, led to the appearance of the effect in experimental results.