Scott Doyle

Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

A novel mechanism for upset is seen in a commercially available 0.25 /spl mu/m 10-T SEE hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions near a single event strike collect the deposited carriers, this new mechanism involves direct drift-diffusion collection at an NFET transistor in conjunction with parasitic bipolar conduction in nearby PFET transistors. The charge collection with the parasitic bipolar conduction compromise the SEE hardened design, thus causing upsets. The mechanism was identified using laser testing and three-dimensional TCAD simulations.

The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve.

A Radiation Hardened 16-Mb SRAM for Space Applications

A new high density, high performance 16-Mb static random access memory (SRAM) is being developed in a 0.15 mum CMOS RH15 technology for use in space and other strategic radiation hardened applications. The SRAM design is implemented in a 1.5 Volt, 0.15 micron and seven-layer metal CMOS technology. Using integrated process features and advanced design techniques, a small cell size of 9.3 mum2 was utilized while achieving a SEU radiation hardness of less than IE-12 upsets/bit-day and a worst-case chip performance of less than 15 ns access time.

The RAD750/sup TM/-a radiation hardened PowerPC/sup TM/ processor for high performance spaceborne applications

BAE SYSTEMS has developed the RAD750/sup TM/, a fully licensed radiation hardened implementation of the PowerPC 750/sup TM/ microprocessor, based on the original design database. The processor is implemented in a 2.5 volt, 0.25 micron, six-layer metal CMOS technology. Employing a superscalar RISC architecture, processor performance of 240 million Dhrystone 2.1 instructions per second (MIPS) at 133 MHz is provided, while dissipating less than six watts of power. The RAD750 achieves radiation hardness of 1E-11 upsets/bit-day and is designed for use in high performance spaceborne applications. A new companion ASIC, the Power PCI, provides the bridge between the RAD750, the 33 MHz PCI backplane bus, and system memory. The Power PCI is implemented in a 3.3 volt, 0.5 micron, five-layer metal CMOS technology, and achieves radiation hardness of <1E-10 upsets/bit-day. This paper describes the implementation of both designs.

PowerPC &#8482; RAD750 &#8482; -A Microprocessor for Now and the Future

The RAD750trade space hardened microprocessor is a fully licensed PowerPCtrade that is identical in architecture, function and operation to the commercial PowerPC 750trade microprocessor. Ongoing performance improvements in both the processor and surrounding devices provide a complete space computer solution for current and future space programs

The Path and Challenges to 90-nm Radiation-Hardened Technology

Radiation effects analysis on a commercial 90-nm CMOS process has been performed to evaluate hardness potential from a process and design perspective, and to identify techniques to promote radiation hardness enhancement towards achieving suitability for low power space applications.

High performance radiation hardened static random access memory (SRAM) design for space applications

Static random access memory (SRAM) product for advanced space applications must demonstrate high performance to meet the ever increasing data rates of space systems and must be radiation hardened to ensure unfettered, reliable operation in the harsh environments of outer space. High performance and radiation hardness are not mutually exclusive. The challenge confronting present day SRAM development is to concurrently achieve both of these objectives. An SRAM design evaluation methodology is described that uncovers limitations on performance, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Simulation model to hardware measurement correlation on two designs of radiation tolerant 4 M SRAM product validates the evaluation methodology. The evaluation methodology described herein can be Universally applied to any SRAM design to ensure that the highest performance potential of the design is realized.

Radiation hardened memories for space applications

Several generations of radiation hardened memory products were developed to support space applications. Both process technology enhancements and specialized design techniques were used to overcome the weaknesses of commercial memories when used in the space environment. The natural advancement of semiconductor technology was used to progressively increase density, enhance performance, and reduce power consumption. Historically, radiation hardened memories for space were fabricated at specialized foundries to achieve strategic levels of radiation hardness for both natural space and military applications. The demand for higher densities and lower cost, however, are pushing for design compatibility with state-of-the-art commercial foundries for 4M SRAM and beyond, and creating a new set of products targeting natural space. Advanced packaging technology is used to improve bit density and reduce weight, both of which are critical for space missions.

Design Considerations for Next Generation Radiation Hardened SRAMs for Space Applications

There is an ever-present focus on increasing the functional density of components used in space electronics, that is, putting more functional capacity in smaller, lighter packages. Packages with small footprints use less board area, potentially reducing system mass. High-density devices may reduce the total required chip count, further eliminating mass and improving system reliability. Low power devices do not overburden the power budget. All of these factors potentially lower the weight of the satellite reducing launch cost and lowering overall operational costs. Increasing the bit density of SRAMs used in space electronics to better realize these positive outcomes presents significant new challenges with respect to radiation hardening of these high-performance, high-density components. BAE systems is designing the next generation of radiation hardened SRAMs. This paper describes the design considerations for advanced radiation hardened SRAMs

Radiation effects on high performance spaceborne electronics

A significant debate has risen from the desire to achieve increased on-board processing capability through the use of commercial components in space. This paper analyses the increasing susceptibility of modern commercial electronics to radiation and considers alternative mitigation approaches.