Reed K. Lawrence

Impact of Ion Energy and Species on Single Event Effects Analysis

Experimental evidence and Monte-Carlo simulations for several technologies show that accurate SEE response predictions depend on a detailed description of the variability of radiation events (e.g., nuclear reactions), as opposed to the classical single-valued LET parameter. Rate predictions conducted with this simulation framework exhibit excellent agreement with the average observed SEU rate on NASAs MESSENGER mission to Mercury, while a prediction from the traditional IRPP method, which does not include the contribution from ion-ion reactions, falls well below the observed rate. While rate predictions depend on availability of technology information, the approach described here is sufficiently flexible that reasonably accurate results describing the response to irradiation can be obtained even in the absence of detailed information about the device geometry and fabrication process.

Single Event Effect Induced Multiple-Cell Upsets in a Commercial 90 nm CMOS Digital Technology

Heavy ion and proton single event upset (SEU) testing has been conducted on static random access memories (SRAM) from two commercial 90 nm technology nodes custom manufactured on epitaxial substrates. The SRAMs were from the same manufacturer; however, the SRAMs utilized two different 90 nm technology process nodes. One 90 nm node was for low power and the other was for performance. Both heavy ion and proton test results indicated multiple-cell upsets. Latchup was not observed in this low voltage epitaxial substrate sample testing. Heavy ion SEU data indicated that above a linear energy transfer of 7 (MeV-cm2)/mg the multiple-cell upsets outnumber the single-cell upsets. Charge sharing is considered the mechanism for multiple-cell upsets.

Soft Error Sensitivities in 90 nm Bulk CMOS SRAMs

Enhanced single event upset (SEU) sensitivity to low energy protons, as much as 5-6 orders of ten, has been observed in 90 nm epitaxial-bulk complementary metal oxide semiconductor (CMOS) static random access memories (SRAM). Enhancements to process and cell design are discussed.

Single-event upset in flip-chip SRAM induced by through-wafer, two-photon absorption

The single-event upset response of a single-event hardened SRAM 10-transistor cell is mapped in two dimensions via carrier injection by two-photon absorption through the back (substrate) surface in a flip-chip mounted 4 Mb SRAM. Using through-wafer carrier injection, charge is deposited into the active regions of the device at well-defined locations in a reproducible manner, and the single-event upset sensitive region of the device is localized to within /spl plusmn/0.3 micrometers.

Radiation Characterization of 512Mb SDRAMs

Two single data-rate 512 Mb SDRAMs have been radiation characterized. The SDRAMs were not from the same manufacturer. The results of total ionizing dose, single event latchup and single event upset are presented. Radiation results show similarities in total ionizing dose level, but demonstrate different modes of failure. One SDRAM experienced single event latchup; whereas the other did not, and for this SDRAM, single event upset with heavy ion and proton testing yielded useable results.

Incremental Enhancement of SEU Hardened 90 nm CMOS Memory Cell

SEU enhancements were introduced into a radiation hardened 90 nm CMOS technology to achieve upset immunity. An incremental enhancement approach that enables various SEU/performance trade-off was demonstrated on the same basic SRAM cell to achieve various degrees of hardness, by the selective utilization of enhancement features. Single event upset testing, as well as MRED simulation, have demonstrated a significant enhancements achieved with a minimal performance penalty.

The Path and Challenges to 90-nm Radiation-Hardened Technology

Radiation effects analysis on a commercial 90-nm CMOS process has been performed to evaluate hardness potential from a process and design perspective, and to identify techniques to promote radiation hardness enhancement towards achieving suitability for low power space applications.

Single Event Gate Rupture Testing on 90 nm Bulk CMOS Deep Trench Oxide Capacitors

Single event gate rupture (SEGR) testing on a deep trench oxide capacitor used for the reduction of single event upsets (SEU) in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology indicates that SEGR was not detected.

Electrical Test Conditioning Influence on Total Ionizing Dose Response of SRAMs

For CMOS, memory array power up (no pattern loaded) is an acceptable TID worst-case dosing condition; however, this condition may not represent a post exposure worst-case electrical characterization.

90-nm Digital Single Event Transient Pulsewidth Measurements

Single event transient (SET) pulsewidth measurements were made on 9SF 90 nm shift registers built with temporal delay latches on epitaxial substrates. Data was gathered using heavy ions from LETs of 9.75 to 58.78 (MeV-cm2)/mg.