Andrew T. Kelly

Single Event Effect Induced Multiple-Cell Upsets in a Commercial 90 nm CMOS Digital Technology

Heavy ion and proton single event upset (SEU) testing has been conducted on static random access memories (SRAM) from two commercial 90 nm technology nodes custom manufactured on epitaxial substrates. The SRAMs were from the same manufacturer; however, the SRAMs utilized two different 90 nm technology process nodes. One 90 nm node was for low power and the other was for performance. Both heavy ion and proton test results indicated multiple-cell upsets. Latchup was not observed in this low voltage epitaxial substrate sample testing. Heavy ion SEU data indicated that above a linear energy transfer of 7 (MeV-cm2)/mg the multiple-cell upsets outnumber the single-cell upsets. Charge sharing is considered the mechanism for multiple-cell upsets.

The Contribution of Low-Energy Protons to the Total On-Orbit SEU Rate

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. Grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or near normal incidence for the bulk circuits.

Incremental Enhancement of SEU Hardened 90 nm CMOS Memory Cell

SEU enhancements were introduced into a radiation hardened 90 nm CMOS technology to achieve upset immunity. An incremental enhancement approach that enables various SEU/performance trade-off was demonstrated on the same basic SRAM cell to achieve various degrees of hardness, by the selective utilization of enhancement features. Single event upset testing, as well as MRED simulation, have demonstrated a significant enhancements achieved with a minimal performance penalty.

The Path and Challenges to 90-nm Radiation-Hardened Technology

Radiation effects analysis on a commercial 90-nm CMOS process has been performed to evaluate hardness potential from a process and design perspective, and to identify techniques to promote radiation hardness enhancement towards achieving suitability for low power space applications.

Quad-core radiation-hardened system-on-chip power architecture processor

Based on the QorIQ® system-on-chip processor architecture from Freescale Semiconductor with additional unique features for space applications, the RAD55xxTM system-on-chip platform integrated circuit can be personalized into multiple processor solutions. The RAD55xx platform includes four 32/64 bit Power Architecture® processor cores, three levels of on-die cache memory, dual interleaved DDR3 DRAM controllers, data path acceleration architecture (DPAA) on-die hardware accelerators, a NAND Flash controller, and high I/O throughput based on serializer/deserializer high speed links. Manufactured at the IBM trusted foundry in 45nm silicon-on-insulator (SOI) process technology with copper interconnect and leveraging the radiation-hardened by design RH45TM technology, the RAD55xx platform optimizes power/performance to deliver processor throughput of up to 5.6 GOPS/3.7 GFLOPS, memory bandwidth of up to 102 Gb/s, and I/O throughput of up to 64 Gb/s. Each of the highly efficient RAD5500™ 64-bit cores offers direct addressability to 64 GB of memory, improves double precision floating point performance, and achieves 3.0 Dhrystone MIPS/MHz. The RAD55xx platform is designed for insertion into systems using the SpaceVPX standard, supporting the RapidIO data plane, SpaceWire control plane, and I2C utility plane. Architectural trades, the development methodology, technical challenges, and single board computer solutions are discussed.

Single Event and Low Dose-Rate TID Effects in the DS16F95 RS-485 Transceiver

Characterization of single event and low dose-rate TID effects in National Semiconductors DS16F95 Radiation-Hardened RS-485 Transceiver is eported. Onset LET for upsetof less than 5 MeV-cm2/mg was observed, and a dependency on operating condition was established. Samples under ELDRS nvestigation adhered to electrical specification after irradiation to 30 krd(Si) at 10 mrd(Si)/s.

Impact of Reference Voltage on the ELDRS Characteristics of the LM4050 Shunt Voltage Reference

Two different reference voltage options (2.5V and 5.0V) of National Semiconductors LM4050WGxxRLQV shunt voltage reference were put through Total Ionizing Dose (TID) testing at High Dose Rate (HDR) and Low Dose Rate (LDR) with different biasing conditions during irradiation and showed different sensitivities to the different dose rates and bias conditions. Another product, DS16F95WxFQMLV, that uses the same wafer fabrication process had a different TID response.

Mitigation of single-event charge sharing in a commercial FPGA architecture

The motivation for single event effects (SEE) analysis and mitigation as part of the process for adaptation of a commercial Field Programmable Gate Array (FPGA) architecture for space-qualified applications is discussed. The interdependent roles of heavy-ion and laser-induced upset evaluation coupled with computer-aided investigations of SEE mechanisms and mitigation techniques in this process are shown to enable a significant reduction in SEE sensitivity of the device, while achieving minimal impact on remanufacturing steps.

Single event effects characterization of BAE systems RADNET™ 1848-PS RapidIO® packet switch

Heavy ion and proton single event effects characterization data on BAE Systems RADNET 1848-PS Application Specific Standard Product are presented. The RADNET 1848-PS is a Serial RapidIO packet switch capable of running at rates up to 3.125 Gbaud. An at-speed SRIO network test for SEE cross section measurement is used to estimate soft error rates for observed upset modes in a reference orbit environment.

Outstanding Conference Paper Award: 2015 IEEE Nuclear and Space Radiation Effects Conference

In this work, experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The upset cross-sections were obtained with accelerated testing using both protons and heavy ions. The proton upset cross-sections were obtained using proton energies ranging from 1 to 500 MeV and the heavy ion data were obtained using ions with effective linear energy transfer (LET) values from 0.6 to 100 . Overall, the SBU data on the 45 nm SOI SRAM showed upset cross-sections-per-bit that were very similar to the cross-sections-per-bit on a 65 nm SOI SRAM for both heavy ion and proton testing. This result continues a trend that has been observed with advanced SOI CMOS SRAMs. In contrast to the SBU data, the MBU data on the 45 nm SRAM showed significantly higher upset cross-sections relative to the 65 nm SRAM. The higher MBU cross-sections were also expected based upon the closer spacing of the nodes in adjacent cells. While the overall trends were anticipated, the major focus of the paper was to understand a diverse range of single event effects that were contributing to the measured upsets. As a function of the incident proton energy, both scattering events and direct ionization upsets were observed. The data also highlighted the unique upset results that are produced at a 90 degree tilt angle. The MBU data showed a very large dependence on the data stored in the SRAM. The data dependence was understood based upon the layout of the SRAM cells and the MBU upsets produced by strikes in common diffusion regions. A detailed analysis of the MBU data showed that almost all of the MBU events occurred in adjacent cells along the bit-lines of the array. This result is very important since the MBU events along the same bit-line will be effectively corrected by error-correctingcode (ECC) circuits. Thus, the higher overall MBU cross-sections that were observed with technology scaling are not a critical issue in SOI SRAMs that use ECC circuits. David F. Heidel received his B.S. degree in physics from Miami University in 1974, and his M.S. and Ph.D. degrees in physics from The Ohio State University in 1976 and 1980 respectively. In 1980, he joined IBM’s Research Division, at the Thomas J. Watson Research Center in Yorktown Heights, NY, working on Josephson superconducting technology. Since