Jason Wei

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-/spl mu/m CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL) and low-bandwidth digitally controlled interpolators. To achieve low jitter while maintaining low power consumption, the dual-loop PLL uses two on-chip linear regulators of different bandwidths, one for the core and the other for the interpolator loop. The prototype chip operates from 400 Mb/s to 4 Gb/s with a bit error rate of <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400-mV output swing driving double terminated links.

Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

To achieve high bit rates link designers are using more sophisticated communication techniques, often turning to 4PAM transmission or decision-feedback equalization (DFE). Interestingly, with only minor modification the same hardware needed to implement a 4PAM system can be used to implement a loop-unrolled single-tap DFE receiver. To get the maximum performance from either technique, the link has to be tuned to match the specific channel it is driving. Adaptive equalization using data based update filtering allows continuous updates while minimizing the required sampler front-end hardware and significantly reduces the cost of implementation in multi-level signaling schemes. A transceiver chip was designed and fabricated in 0.13 /spl mu/m CMOS process to investigate dual-mode operation and the modifications of the standard adaptive algorithms necessary to operate in high-speed link environments.

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

A high-speed interface circuit delivering 660 MB/s data is implemented as a byte-wide I/O bus-interface cell. The interface contains low-swing input receivers, controlled-current output drivers, and clock-recovery circuits. The circuits perform well in noisy environments such as microprocessors, and withstand LdI/dt noise generated in high-inductance packages such as PQFPs. The interface is implemented as a full-custom ASIC library mega-cell, reducing area and power over gate-array approaches. An advanced CAD methodology is used to easily port the analog circuits and high-speed digital circuits in the interface cell to multiple-fabrication process technologies. The cell is used as an interface for ASIC-to-DRAM communication and for ASIC-to-ASIC communication, for point-to-point links and for bused links.

A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

A quad high-speed transceiver cell is designed and implemented in 0.13 /spl mu/m CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400 Mb/s to 4 Gb/s with a bit error rate <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400 mV output swing driving double terminated links.

A 2.6-GByte/s multipurpose chip-to-chip interface

A 2.6 GByte/s megacell that interfaces to single or double byte wide DRAMs or logic chips is implemented using 0.35-0.18 /spl mu/m CMOS technologies. Special I/O circuits are used to guarantee 800 Mbit/s/pin data rate. Microwave PC board design methodologies are used to achieve the maximum possible interconnect bandwidth.

A 2.6 GB/s multi-purpose chip-to-chip interface

A high-speed interface cell delivers 800 Mb/s/pin data transfer rate on a 26b wide I/O interface consisting of a dual-byte data field and a byte-wide command field. For 2.6 GB/s data rate, a 400 MHz clock recovery circuit guarantees the timing margin for transferring 800 mV swing data at both clock edges over the I/O interface. Data from the high speed interface is internally deserialized to provide a 100 MHz (f/4) ASIC clock interface. A test chip contains three megacells and built-in clock synchronization circuits to ensure proper data transfer between the three megacells with minimal impact on latency. Controlled impedance buses, referred to as channels, with careful PCB layout ensure 800 Mb/s/pin data rate on-board for ASIC-to-ASIC or ASIC-to-DRAM system configuration.

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

A fast-wakeup bang-bang LC digital phase-locked loop (DPLL) suitable for low-power wireline applications is presented. The PLL uses a novel oscillator design to generate eight output phases using magnetic coupling. The fast-wakeup feature improves power efficiency by allowing PLL power-cycling while accommodating latency requirements. Fast lock upon wakeup is achieved by calibrating the phase of the feedback clock with respect to the reference clock using a first-order loop and is further assisted by on-the-fly adjustment of loop parameters. The eight-phase output clock is generated using a loop of four digitally-controlled oscillators (DCOs) that are magnetically coupled through a passive structure. This structure enables magnetic coupling among oscillators with 2x area improvement over the prior art. As a result, in addition to eliminating the noise and parasitic capacitance of active coupling devices, the compact design reduces parasitic wiring capacitance, which is a significant limitation in high-frequency coupled oscillator design. Implemented in a 40 nm CMOS technology, the design achieves a 40-reference-cycle (100 ns) lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° quadrature phase error up to 25 GHz. Measured PLL jitter is 392 fs (integrated from 100 kHz to 100 MHz) at 25 GHz while drawing 64 mW of power, 23 mW of which is consumed in the multiphase DCO. The DPLL occupies a total area of 0.1 mm2.

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.

Design challenges for high performance and power efficient graphics and mobile memory interfaces

Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in todays systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural and circuit-level design tradeoffs. In this paper, we compare two different memory interface design examples, one from each area operating at 16Gbps and 3.2Gbps per pin respectively, and highlight their major differences in terms of driver and receiver design, as well as clock generation and distribution. We will also discuss some of the problems facing future generations of memory interfaces that push the limits of performance and power efficiency.