Vijay Gadde

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

A fast-wakeup bang-bang LC digital phase-locked loop (DPLL) suitable for low-power wireline applications is presented. The PLL uses a novel oscillator design to generate eight output phases using magnetic coupling. The fast-wakeup feature improves power efficiency by allowing PLL power-cycling while accommodating latency requirements. Fast lock upon wakeup is achieved by calibrating the phase of the feedback clock with respect to the reference clock using a first-order loop and is further assisted by on-the-fly adjustment of loop parameters. The eight-phase output clock is generated using a loop of four digitally-controlled oscillators (DCOs) that are magnetically coupled through a passive structure. This structure enables magnetic coupling among oscillators with 2x area improvement over the prior art. As a result, in addition to eliminating the noise and parasitic capacitance of active coupling devices, the compact design reduces parasitic wiring capacitance, which is a significant limitation in high-frequency coupled oscillator design. Implemented in a 40 nm CMOS technology, the design achieves a 40-reference-cycle (100 ns) lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° quadrature phase error up to 25 GHz. Measured PLL jitter is 392 fs (integrated from 100 kHz to 100 MHz) at 25 GHz while drawing 64 mW of power, 23 mW of which is consumed in the multiphase DCO. The DPLL occupies a total area of 0.1 mm2.