Ping-Hsuan Hsieh

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1-3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain these data rates. This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps.

Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques and can be exploited to compensate for the noise coupling caused by the parasitic capacitance in the loop filter of a phase-locked loop (PLL). The proposed CMOS ring oscillator is designed and implemented with a charge-pump based PLL in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 5.12-GHz output clock is reduced from 6.41 ps to 2.38 ps while subject to supply noise at 90 MHz.

A 0.003 mm

This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction technique based on the non-binary search are proposed to tackle the static and dynamic non-idealities attributed to capacitor mismatch and insufficient DAC settling. The conversion speed is enhanced, and the power and area of the DAC are also reduced by 40% as a result. In addition, a switching scheme lifting the input common mode of the comparator is proposed to further enhance the speed. Moreover, the comparator employs multiple feedback paths for an enhanced regeneration strength to alleviate the metastable problem. Occupying an active area of 0.003 mm 2 and dissipating 0.68 mW from 1 V supply at 240 MS/s in 28 nm CMOS, the proposed design achieves an SNDR of 57 dB with low-frequency inputs and 53 dB at the Nyquist input. This corresponds to a conversion efficiency of 4.8 fJ/c.-s. and 7.8 fJ/c.-s. respectively. The DAC switching technique improves the INL and DNL from +1.15/-1.01 LSB and +0.92/-0.28 LSB to within +0.55/-0.45 LSB and +0.45/-0.23 LSB, respectively. This ADC is at least 80% smaller and 32% more power efficient than reported state-of-the-art ADCs of similar resolutions and Nyquist bandwidths larger than 75 MHz.

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A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces.

10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

A method to minimize the supply sensitivity of a CMOS ring oscillator is proposed through joint biasing of the supply and the control voltage. The technique can supplement a number of common supply rejection techniques. The proposed CMOS ring oscillator is designed and implemented with a charge-pump based phase-locked loop in 65-nm technology to demonstrate the robustness against the supply fluctuation. Taking advantage of the negative static supply sensitivity of the ring oscillator with proper combination of the bias voltages, the rms jitter of the 4-GHz output clock is reduced from 10.66-ps to 5.04-ps while subject to switching noise with magnitude of 2.5% of the supply voltage at 150-MHz. Furthermore, more than 4.5times of reduction in the power consumption is achieved.

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS technologies due to their ease of integration and scalability with digital logic. However, digital quantization results in larger steady-state systematic jitter, or dithering. High resolution is needed to control the oscillator to minimize the dithering. This brief proposes a simple method to reduce the frequency-resolution requirement. The method allows for substantial reduction in the hardware complexity without sacrificing the DPLLs dynamic characteristics

Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage

Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.

Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs

Impulse radar is a promising method for achieving high-range resolution and multi-path immunity for ranging and localization applications [1], [2]. Impulse radar sends signals with short duration and spreads signal power over a large bandwidth. Favorable features of impulse radar are minor interference with other wireless systems as well as high immunity to nearby radio signals. Thus, impulse radars are compatible with the harsh environments where intensive radio services are operating. In conjunction with the advantages of high integration and low cost in mass production from CMOS technology, more ubiquitous utilizations are feasible for CMOS impulse radars.

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

This paper examines several transfer curves of the phase detector in a digital phase-locked loop and illustrates the benefits of applying non-linearity to the phase transfer characteristics. Taking advantage of the programmability of the digital implementation, the proposed technique shows a better trade-off between the acquisition speed and the steady-state dithering jitter performance.

28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS

A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels. Measurements of a test chip fabricated in 32nm SOI CMOS technology demonstrate 1.4-pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9-pJ/b efficiency over 20” Megtron-6 PCB traces.