Jean Jimenez

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

ESD RF protections in advanced CMOS technologies and its parasitic capacitance evaluation

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to down-scaling which introduces a reduction of the intrinsic robustness. Moreover, another challenge is the RF ESD protection in analogue IO pad. Thus, when you merge both topics the challenges are major. This paper shows a methodology, tools and silicon measurements of ESD RF parasitic capacitance in C65nm & C45nm to reach 10Ghz & 20Ghz bandwidth for 1kV & 2kV HBM.

Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology

The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be compared. Also, the power pad clamps in 1 pitch IO are qualified through 100ns TLP. Silicon result show that ESD robustness reaches 4kV HBM, 200V MM and 500V CDM for a 64 BGA package. IO power pads are also immune to Latch Up and power sequence.

Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies

Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

SRAM bitcell optimizations have been demonstrated in 28nm High-k Metal Gate UTBB (Ultra-Thin Body and BOX) FD-SOI technology. The back-gate terminal biasing leads to forward or reverse bias of the transistors and has been used to improve the bitcell electrical metrics. The derived 6T bitcell variants show a gain of 67% (25%) in cell current at 0.6V (1V), 45% reduction in write time at 0.6V, along with a gain in either write margin or static noise margin. Two 4T load-less bitcell variants using back-gate bias have been fabricated and compared for performance, power and stability margins. The back-gate biasing concept has been extended to optimize 8T, 10T bitcells and their simulation results are also presented.

Transmission line with 2-kV HBM broadband ESD protection using BIMOS and SCR in advanced CMOS technologies

Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharges (ESD) issues become more significant. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of the RFICs. ESD protection size dimensions are also an issue to protect RFICs. This paper presents measurements results of ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology

FDSOI technology with ultra-thin body and box (UTBB) provides a back-gate terminal which can be effectively used to forward bias or reverse bias the MOSFET. Using the back-gate terminals, the SRAM 6T bitcell has been modified resulting in four variants which are differently capable of better read and write margins, enabling lower operating voltage. At the same time, all the variants give improvement in the cell current and write time. The four variants have been fabricated in 28nm High-K Metal-Gate FDSOI technology and benchmarked against the standard 6T bitcell. There is a gain of 67%(25%) in cell current at 0.6V(1V) and 45% reduction in write time at 0.6V. Along with this, a gain in write margin or a gain in static noise margin can be chosen from the various variants. Applicability of read stability and write assist techniques to these bitcells has also been discussed.

New Beta-Matrix topology in CMOS32nm and beyond for ESD/LU improvement

This paper is focused on the optimization of Beta-Matrix power device to protect thin oxide GO1 =1 V and thick oxide G02=1.8V. The study investigates Beta-Matrix topology and particularly the impact of elementary pattern on device behavior. This work is mainly carried on 3D TCAD simulations. The best configurations, with lower voltage triggering have been realized in CMOS32nm high k metal gate and characterized thanks Transmission Line Pulse (TLP) with 100ns width.

ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology

The aim purpose of this study is to evaluate the ESD protection using BIMOS transistor in the RF and fast swing application for advanced CMOS technology in 32 nm high k metal gate & bulk substrate. The ESD target is 1kV HBM and the RF one is 100 GHz broadband. Moreover the DC behavior is also performed. Thus, the challenge here is to be efficient in ESD protection with a minimum of parasitic capacitance. To address these specifications the solution discussed in this paper uses the Bimos transistor characterized through TLP and DC measurements. A RF model is proposed and calibrated thanks to S parameters. Moreover, the R parameter range is investigated to the full 100GHz frequency range.

High swing low capacitance ESD RF protections in advanced CMOS technologies

High speed interface are more and more integrated on System On Chip (SOC) and need efficient Electro Static Discharge (ESD) protections devices. The challenge is to ensure high level of ESD protection in a very large bandwidth to address HDMI, SATA, DisplayPort and USB interfaces. Another challenge is to address a large panel of technology nodes as high seed interfaces are implemented in various technologies. This paper shows performances of RF protection devices in term of ESD robustness and frequency response. Experimental results are presented and compared in 250 nm, 130 nm and 40 nm technologies nodes and shows ability of protections to sustain 2kV Human Body Model (HBM) with 30Ghz bandwidth in large voltage dynamic range.