D. Marin-Cudraz

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

Innovative ESD protections for UTBB FD-SOI technology

We present an innovative set of UTBB (Ultra-Thin Body and BOX) ESD protection devices, which achieves remarkable performance in terms of leakage current and triggering control. Ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V <; Vt1 <; 2.6V) capability are demonstrated. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.

ESD robustness of FDSOI gated diode for ESD network design: Thin or thick BOX?

The robustness against Electrostatic Discharge (ESD) events of gated diodes, fabricated in CMOS 45nm FDSOI technology, is compared for 10nm and 145nm Buried Oxide (BOX) thickness. It is shown that the performance of devices for co-design on thin BOX is improved thanks to a better thermal dissipation: A gain of 1.6 on the robustness was found.

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. The paper presents a comparison between four ESD protections in CMOS 32 nm node. Dynamic and static triggering circuits are investigated and SCR and bi-SCR are compared. Each structure is characterized through TLP and protects up to 2 kV HBM stresses.

A sharp-switching gateless device (Z3-FET) in advanced FDSOI technology

A systematic study of a novel band modulation device (Z3-FET: Zero gate, Zero swing slope and Zero impact ionization) fabricated in most advanced Fully Depleted Silicon-On-Insulator technology is presented. Since the device has no front gate, the operation mechanism is controlled by two buried ground planes. Characteristics such as sharp switching, low leakage, and controllable triggering are measured and discussed. We explore several variants (thin and thick silicon film) and show promising results in terms of high current and switching performance.

New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology

The aim of this paper is to introduce a new design of modular bi-directional power switch for 28nm Ultra Thin Body and BOX (UTBB) Full Depleted (FD) SOI advanced CMOS technology and beyond. Moreover, this proposed solution is self-protected against ElectroStatic Discharge (ESD). The first challenge is to obtain a robust symmetrical elementary power device compatible with this technology and with a silicon area optimization. The second one is to provide a new design to trigger this power device. The last challenge is to be efficient in term of ESD robust without additional protection device. These specifications are reached thanks to a Triac (dual back to back SCR) power device in matrix and BIMOS transistors used in a new trigger solution. The study is performed through the 2D-3D TCAD simulation and a test chip is performed in 28nm FDSOI with silicon demonstrator. Measurements are done in DC sweep condition, in high current pulse with 100ms time width. It also includes Transmission Line Pulse (TLP) with 100ns time width to characterize and qualify this design and topology in ESD range time event.

Innovative high-density ESD protection device in state of the art UTBB FDSOI technologies

For the first time, we demonstrate an innovative way to build ESD protection in FDSOI technologies. This protection is comprised of two stacked devices one on the other: a bottom bulk-thyristor and a top thin film triggering device. Low leakage current, tunable triggering voltage and high current capability are highlighted.

ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology

The aim purpose of this study is to evaluate the ESD protection using BIMOS transistor in the RF and fast swing application for advanced CMOS technology in 32 nm high k metal gate & bulk substrate. The ESD target is 1kV HBM and the RF one is 100 GHz broadband. Moreover the DC behavior is also performed. Thus, the challenge here is to be efficient in ESD protection with a minimum of parasitic capacitance. To address these specifications the solution discussed in this paper uses the Bimos transistor characterized through TLP and DC measurements. A RF model is proposed and calibrated thanks to S parameters. Moreover, the R parameter range is investigated to the full 100GHz frequency range.

Ultracompact ESD Protection With BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip.