Johan Bourgeat

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology

The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be compared. Also, the power pad clamps in 1 pitch IO are qualified through 100ns TLP. Silicon result show that ESD robustness reaches 4kV HBM, 200V MM and 500V CDM for a 64 BGA package. IO power pads are also immune to Latch Up and power sequence.

Beta-Matrix ESD network: Throughout end of placement rules?

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some constraint on IO and particularly on the frame and the placement in IO ring. In this context we develop and propose an ESD network with Beta-Matrix power device and its own trigger circuit which are integrated in each IO. We obtain a new local strategy which allows removing all IO placement constraint.

New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology

The aim of this paper is to introduce a new design of modular bi-directional power switch for 28nm Ultra Thin Body and BOX (UTBB) Full Depleted (FD) SOI advanced CMOS technology and beyond. Moreover, this proposed solution is self-protected against ElectroStatic Discharge (ESD). The first challenge is to obtain a robust symmetrical elementary power device compatible with this technology and with a silicon area optimization. The second one is to provide a new design to trigger this power device. The last challenge is to be efficient in term of ESD robust without additional protection device. These specifications are reached thanks to a Triac (dual back to back SCR) power device in matrix and BIMOS transistors used in a new trigger solution. The study is performed through the 2D-3D TCAD simulation and a test chip is performed in 28nm FDSOI with silicon demonstrator. Measurements are done in DC sweep condition, in high current pulse with 100ms time width. It also includes Transmission Line Pulse (TLP) with 100ns time width to characterize and qualify this design and topology in ESD range time event.

New Beta-Matrix topology in CMOS32nm and beyond for ESD/LU improvement

This paper is focused on the optimization of Beta-Matrix power device to protect thin oxide GO1 =1 V and thick oxide G02=1.8V. The study investigates Beta-Matrix topology and particularly the impact of elementary pattern on device behavior. This work is mainly carried on 3D TCAD simulations. The best configurations, with lower voltage triggering have been realized in CMOS32nm high k metal gate and characterized thanks Transmission Line Pulse (TLP) with 100ns width.

High swing low capacitance ESD RF protections in advanced CMOS technologies

High speed interface are more and more integrated on System On Chip (SOC) and need efficient Electro Static Discharge (ESD) protections devices. The challenge is to ensure high level of ESD protection in a very large bandwidth to address HDMI, SATA, DisplayPort and USB interfaces. Another challenge is to address a large panel of technology nodes as high seed interfaces are implemented in various technologies. This paper shows performances of RF protection devices in term of ESD robustness and frequency response. Experimental results are presented and compared in 250 nm, 130 nm and 40 nm technologies nodes and shows ability of protections to sustain 2kV Human Body Model (HBM) with 30Ghz bandwidth in large voltage dynamic range.

ESD protection structure enhancement against Latch-Up issue using TCAD simulation

During IO qualifications LUP tests in CMOS28nm Bulk technology, undesired ESD structure triggering has been found to be the root cause of LUP fails. Deeper test analysis identifies the combination of IOs abutment sequence that generate the fail. The understanding of the phenomenon is investigated through a specific TCAD simulation set-up.

Ultracompact ESD Protection With BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip.

Self-ESD-protected transmission line broadband in CMOS28nm UTBB-FDSOI

Advanced CMOS Technologies, and particularly Ultra-Thin Body and BOX Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology provide good performances for analog high frequency and ultra-low power applications. We present in this paper self-ESD-protected transmission lines based on two different ESD strategies. Specific ESD protections based on bidirectional SCR (bi-SCR) are directly embedded on the transmission lines.