Boris Heitz

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

Geometrical impact on RF performances of broadband ESD self protected transmission line in advanced CMOS technologies

Advanced CMOS technologies provide an easy way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharge (ESD) issues become more significant. Unfortunately, parasitic capacitance of the ESD protection limits the operating bandwidth of the RFICs. The size (i.e. die area) of ESD protection is also of concern in RFICs. This paper presents results of transmission line with ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

Transmission line with 2-kV HBM broadband ESD protection using BIMOS and SCR in advanced CMOS technologies

Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharges (ESD) issues become more significant. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of the RFICs. ESD protection size dimensions are also an issue to protect RFICs. This paper presents measurements results of ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology

The aim purpose of this study is to evaluate the ESD protection using BIMOS transistor in the RF and fast swing application for advanced CMOS technology in 32 nm high k metal gate & bulk substrate. The ESD target is 1kV HBM and the RF one is 100 GHz broadband. Moreover the DC behavior is also performed. Thus, the challenge here is to be efficient in ESD protection with a minimum of parasitic capacitance. To address these specifications the solution discussed in this paper uses the Bimos transistor characterized through TLP and DC measurements. A RF model is proposed and calibrated thanks to S parameters. Moreover, the R parameter range is investigated to the full 100GHz frequency range.

High swing low capacitance ESD RF protections in advanced CMOS technologies

High speed interface are more and more integrated on System On Chip (SOC) and need efficient Electro Static Discharge (ESD) protections devices. The challenge is to ensure high level of ESD protection in a very large bandwidth to address HDMI, SATA, DisplayPort and USB interfaces. Another challenge is to address a large panel of technology nodes as high seed interfaces are implemented in various technologies. This paper shows performances of RF protection devices in term of ESD robustness and frequency response. Experimental results are presented and compared in 250 nm, 130 nm and 40 nm technologies nodes and shows ability of protections to sustain 2kV Human Body Model (HBM) with 30Ghz bandwidth in large voltage dynamic range.

Self-ESD-protected transmission line broadband in CMOS28nm UTBB-FDSOI

Advanced CMOS Technologies, and particularly Ultra-Thin Body and BOX Fully Depleted Silicon on Insulator (UTBB-FDSOI) technology provide good performances for analog high frequency and ultra-low power applications. We present in this paper self-ESD-protected transmission lines based on two different ESD strategies. Specific ESD protections based on bidirectional SCR (bi-SCR) are directly embedded on the transmission lines.

Model and measurements of a transmission line with integrated symmetrical 1-kV HBM broadband ESD Protection in advanced CMOS technologies

Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharges (ESD) issues become more significant. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of the RFICs. ESD protection size dimensions are also an issue to protect RFICs. This paper presents an ESD solution and model able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies.