Lucian Barbut

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

In this paper, we investigate the technological constrains and design limitations of ultrathin body junctionless double gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as a guideline for technology optimization of JL DG MOSFETs.

A Common Core Model for Junctionless Nanowires and Symmetric Double-Gate FETs

In this paper, we evidence the link between the planar and cylindrical junctionless field effect transistors (JL-FETs) from the electrostatics and current point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for JL nanowires can be mapped on the planar double-gate topology generating only negligible mismatch, meaning that both devices can share the same core model as far as long channels are considered. These preliminary results are a first step toward a unification of compact models for JL-FETs.

Trans-Capacitance Modeling in Junctionless Symmetric Double-Gate MOSFETs

We have developed a closed-form solution for trans-capacitances in long-channel junctionless double-gate (JL DG) MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with technology computer-aided design simulations. According to this paper, a complete intrinsic capacitance network is obtained, which represents an essential step toward ac analysis of circuits based on junctionless devices.

Modeling Asymmetric Operation in Double-Gate Junctionless FETs by Means of Symmetric Devices

This paper aims to model asymmetric operation in double-gate junctionless FETs. Following a rigorous approach, we find that asymmetric operation can be simulated by combining two symmetric junctionless FETs, what we call the virtual symmetric device concept. In addition to the benefits in terms of compactness and coherence, such equivalence is used to develop a complete charge-based model for independent double-gate junctionless architectures, including mismatch in gate capacitance and material work functions.

Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion

In this brief, we have developed a charge-based model for the symmetric double-gate junctionless (JL) field effect transistor (FET) that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of JL FETs beyond the domain of operation for which they have been designed. In addition, to its interest for providing technology design rules, the new model is able to explain the unexpected increase in the gate capacitance when biasing the device in deep depletion as well as the theoretical limit for the OFF-current in deep depletion.

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

This paper investigates a new method to measure mobility in nanowires. With a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low-dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose to extract the drift mobility in nanowires by measuring a variation of the electric current caused by the presence of a magnetic field, in a specific nanowire network topology. This method overcomes the limitations inherent to the standard Hall effect technique and might open the way to a more precise and simple measurement of mobility in nanowires, still a matter for intensive research.

Towards fabrication of Vertical Slit Field Effect Transistor (VeSFET) as new device for nano-scale CMOS technology

This paper proposes a CMOS based process for Vertical Slit Field Effect Transistors. The central part of the device, namely, the vertical slit, is defined by using electron beam lithography and silicon dry etching. In order to verify the validity and the reproducibility of the process, devices having the slit width ranging from 16 nm to 400 nm were fabricated, with slit conductance in the range 0.6 to 3 milliSiemens, in agreement with the expected values.