Baozhen Li

Reliability challenges for copper interconnects

Abstract In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low- k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.

Modeling of time-dependent non-uniform dielectric breakdown using a clustering statistical approach

We report a time-dependent clustering model for non-uniform dielectric breakdown. Its area scaling and low-percentile scaling properties are rigorously investigated. While at high percentiles non-uniform area scaling dominates, the model restores the weakest-link characteristics at low percentiles relevant for reliability projection. As a result, we develop a comprehensive methodology for the parameter extraction and projection methodology for non-uniform dielectric breakdown. Excellent agreement is obtained between the model and the experimental data of back-end-of-line low-k dielectrics and front-end-of-line gate dielectrics, suggesting a wide range of applications of this model in the field of dielectric breakdown reliability.

Line depletion electromigration characterization of Cu interconnects

Specific details of both fabrication process and geometry of Cu interconnects result in different electromigration (EM) fail modes. This paper discusses EM characteristics of line depletion stress, i.e., for the case of electrons flowing from a via above into a Cu line through a Cu diffusion barrier to cause voiding in the line. For electrons flowing from a W via, for example to a Cu line above, electrical redundancy (i.e., a current shunt layer) exists due to the overlap of line bottom liner over the top of the via, such that a current path still exists in the event that the Cu is removed. When electrons flow from a via above down to a Cu line, the redundancy characteristics can be very different for different via/line layouts, and can result in different EM fail distributions. The solid contact between via above and the liner of the line below can result in tight fail distributions, while weak contact or lack of contact between the via above and the liner of the line below can cause broad (high sigma), or even multimode fail distributions. A few examples and their implications on robust interconnect design are presented. The relation between void size and liner redundancy characteristics is also discussed.

Influence of underlying interlevel dielectric films on extrusion formation in aluminum interconnects

Knowledge of the mechanical properties of interlevel dielectric films and their impact on submicron interconnect reliability is becoming more and more important as critical dimensions in ultralarge scale integrated circuits are scaled down. For example, lateral aluminum (Al) extrusions into spaces between metal lines, which become more of a concern as the pitches shrink, appear to depend partially on properties of SiO2 underlayers. In this article nanoindentation, wafer curvature, and infrared absorbance techniques have been used to study the mechanical properties of several common interlevel dielectric SiO2 films such as undoped silica glass using a silane (SiH4) precursor, undoped silica glass using a tetraethylorthosilicate precursor, phosphosilicate glass deposited by plasma-enhanced chemical vapor deposition and borophosphosilicate glass (BPSG) deposited by subatmosphere chemical vapor deposition. The elastic modulus E and hardness H of the as-deposited and densified SiO2 layers are measured by nanoi...

Electromigration-resistance enhancement with CoWP or CuMn for advanced Cu interconnects

Suppressing Cu diffusion along the Cu/Cap interface has proven to be one of the most effective ways to enhance the electromigration (EM) resistance of advanced Cu interconnects. Two methods, depositing a thin layer of CoWP on the Cu surface and doping the Cu seed layer with Mn, are presented in this paper. While each effectively enhanced the EM performance, they behaved somewhat differently in improving the line-depletion and via-depletion EM performance. CoWP functioned primarily as a Cu surface modifier and did not alter the Cu diffusion behavior below the surface, making Cu interconnects capped with CoWP very sensitive to defects in the via. As a result, the hardware processed with CoWP had greatly increased EM failure times, but also had large variability in failure times and activation energy. On the other hand, the hardware with the CuMn seed layer relied on Mn segregation to the Cu surface to slow down the Cu diffusion, plus Mn also may have diffused to grain boundaries and defective areas of the liner. Although the EM failure times of Cu interconnects with CuMn seed in some cases were not as long as those with CoWP, the variability and sensitivity to process defects was reduced.

Critical ultra low-k TDDB reliability issues for advanced CMOS technologies

During technology development, the study of ultra low-k (ULK) TDDB is important for assuring robust reliability. As the technology advances, several critical ULK TDDB issues were faced for the first time and needed to be addressed. First, the increase of ULK leakage current noise level induced by soft breakdown during stress was observed. Second, it was found that ULK had lower field acceleration than dense low-k. Such process and material dependences of ULK TDDB kinetics were investigated, and an optimal process to improve ULK voltage acceleration was identified. Last, as the reliability margin for ULK TDDB of via-related structures is greatly reduced at advanced CMOS technologies, a systematic study of via TDDB regarding area scaling and test structure design was conducted. It was found that only a portion of the total vias possibly determines the low-k via TDDB. A new “fatal” via ratio concept is introduced to replace the as-designed area ratio for TDDB area scaling in structures with vias, and a methodology called shift and compare (S&C) is proposed to determine the “fatal” via ratio.

Impact of via-line contact on Cu interconnect electromigration performance

Damascene processing creates special features for copper interconnect electromigration (EM). Though the fast Cu diffusion path is along the interface between Cu and the top cap layer, the early EM fails are often associated with vias, either by voiding in the via (via depletion), or by voiding underneath the via (line depletion). While most of the early EM fails for via depletion are related to the liner quality in vias, for line depletion EM the contact configuration between the via and the underlying line is critical to the failure characteristics. The contact between the via and the line liner below can effectively prevent or minimize open-circuit type EM failures. Redundant vias can significantly improve the EM performance in both the median failure time (t/sub 50/) and the distribution shape (sigma, /spl sigma/), depending on the arrangement of these vias relative to the line below. This paper presents an EM study of Cu interconnects with various via/line contact configurations. Results from single via and multiple via contacts, with and without redundancy to the underlying lines, are discussed.

Via-depletion electromigration in copper interconnects

Via-depletion electromigration was studied under a number of conditions in a 65-nm technology. Observed failure distributions were either single mode or bimodal, depending on the structural configuration. The distribution and the time to fail for the early-fail mode of the bimodal distributions varied with linewidth, via redundancy, and via current density. Additionally, it was observed that for bimodal failure distributions, the length of the extension of the line past the via determined the fraction of early fails in the via. The bimodal behavior was suppressed by optimization of the via liner deposition process

Characterization and reliability of TaN thin film resistors

TAN resistors are commonly used in RFIC applications and are gaining acceptance in traditional CMOS designs. TAN materials, frequently used in fabrication of Cu interconnects can easily be applied to the fabrication of thin film resistors. Deposition and integration of the films may be well controlled to produce a high precision resistor, and the temperature coefficient of resistance (TCR) characteristics of the film make it ideally suited for application across a large temperature range. While the time zero characteristics of the device are well understood, of equal importance are the device reliability properties. In this paper traditional film characteristics such as resistance distributions and TCR characteristics are presented. A voltage ramp stress is employed to identify the critical current A constant voltage stress at high temperature is utilized for reliability evaluation. Based on the stress results, a reliability degradation model is derived to express the relationship between stress condition, resistance change, and lifetime. The results demonstrate that the TAN thin film resistor is reliable over traditional IC operating ranges. While TAN resistors are robust, application conditions of the resistor typically result in significant resistive joule heating. The joule heating effects on the resistor are included in the resistor degradation model. The effects of the joule heating on reliability for neighboring structures must also be considered. The effective result is that the maximum allowed use current of the resistor might be dictated by the resistive joule heating and not necessarily the resistor reliability itself. The effect of the joule heating on neighboring structures is a subject itself and will not be covered in this paper.

Electromigration challenges for advanced on-chip Cu interconnects

Abstract As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.