Nazmul Habib

Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test

Use of a Scaling Parametric Macro (SPM) provides more accurate product level environment parametric information than scribe line (Kerf) structures. This paper compares drive current (Ion) data obtained with the SPM macros to scribe line structure Ion measurements. SPM macros provide less variation than scribe line structures. Since SPM is small enough to be included in all products, the SPM macro provides improved Ion product screening

Accurate chip leakage prediction: Challenges and solutions

A systematic method is proposed to address modeling challenges in accurate chip level leakage prediction, namely a precise total leakage width count method, a simple model to quantify leakage uplift caused by systematic across-chip variation, and a consistent model to capture 3-sigma leakage and leakage spread at fixed performance.

Deep trench capacitor in three dimensional through silicon via keepout area for electrostatic discharge protection

To fully enable and leverage the power of advanced processors, products must have abundant cache memory with much shorter access paths without increasing chip size. This requires growing products in the z-direction by building stacked chips (3D chips). To optimize 3D product costs, the area consumed by other processing requirements such as electrostatic discharge (ESD) protection needs to be as efficient as possible. Placing ESD structures made with deep trench capacitors in three dimensional Through silicon via keepout areas optimizes silicon area since these structures enable placement of ESD devices in space that would otherwise not be used.

Improved yield through use of a Scalable Parametric Measurement macro

Incorporating a scalable parametric measurement (SPM) macro in semiconductor products enables N to P ratio screening at wafer test where each die can be tested. While in line scribe line measurements provide valuable feedback to correct manufacturing problems, in line test sample sizes and the need to disposition entire wafers limit the usefulness of this technique as a product screen. Functional patterns applied at module test provide a measure of protection against escapes to system level, but module yield loss results in higher cost than wafer yield loss because of the added loss of package and module test costs. Use of a SPM macro for N to P ratio disposition maximizes yield and minimizes false rejects and false accepts.