Jeff Burleson

Amplifier gain enhancement with positive feedback

The use of positive feedback as a solution to maximum intrinsic gain degradation in scaled technologies is discussed. Criteria for increasing gain while keeping the system stable are derived in terms of a non-ideal amplifier model. The amplifier model, in an attempt to standardize positive feedback analysis on generic amplifiers, includes non idealities that traditional feedback theory does not, including finite input impedance and non-zero output impedance. This treatment shows that as amplifier open loop gain decreases, positive feedback can more readily be applied to increase that gain at a cost of a slightly more than one-to-one tradeoff with the amplifier bandwidth and minimal area overhead. This analysis shows that the concept of positive feedback is most useful in high bandwidth single stage amplifiers where gain is at a minimum. The theory is applied to a differential amplifier in 65 nm technology and is shown to increase the DC gain by more than 25 dB in silicon measurements.

Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs

In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFETs at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S/sub 11/ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S/sub 11/ in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logics 0.18 /spl mu/m and 0.11 /spl mu/m processes, across five different wafers.

Maximum intrinsic gain degradation in technology scaling

Aggressive device scaling has begun to pose significant problems to the analog design community. For the most part, digital circuitry benefits from the effects of scaling in terms of both faster speeds and decreased power consumption with the exception gate leakage becoming significant. A recent push towards system on a chip (SOC) designs in which both digital and analog components of a system co-exist on the same monolithic substrate has forced many analog designs into these scaled technologies. The effects of scaling have not been as beneficial to the analog component as it has to their digital counterparts.

AC-coupling strategy for high-speed transceivers of 10Gbps and beyond

AC coupling in a transmission link is preferred and often required for the functioning of high speed transceivers. But at data rate of 1OGbps and beyond, both the external AC coupling and the conventional on-chip AC coupling approaches bring in heavy burden that pushes to the fundamental limits and are difficult to afford. This paper examines the AC-coupling methods for multi-Gb/s transceivers, and points out the impairments in the existing implementations. A hybrid structure offering both the signal-bump and the AC-capacitor functions under the stringent return-loss requirements of a 1OGb/s+ I/O is proposed and implemented in 65nm standard CMOS. A sizeable 5.1pF AC capacitor is measured with ultra low parasitic expense ratio of less than 120fF.

Using positive feedback to overcome g m r o limitations in scaled CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled technologies is discussed. Criteria for increasing gain while keeping the system stable are derived in terms of traditional feedback theory as well as a modified amplifier model. The amplifier model, in an attempt to standardize positive feedback analysis on generic amplifiers, includes non idealities that traditional feedback theory does not, including finite input impedance and non-zero output impedance. Both treatments show that as amplifier open loop gain decreases, positive feedback can more easily be applied to increase that gain at a cost of a slightly more than one-to-one tradeoff with the amplifier bandwidth. This analysis shows that the concept of positive feedback is most useful in high bandwidth single stage amplifiers where gain is at a minimum. It is applied to a differential stage in 65 nm technology and is shown to increase the gain from 12.61 dB to 27.25 db.

Accurate performance prediction of multi-GHz CML with data run-length variations

Accurate prediction of multi-GHz CML dependency on data run-time variation requires precise device models at those frequencies. Inconsistencies caused in the CML by run-time variations of the input data are clearly demonstrated. Further, an accurate RF MOSFET model that can be dynamically changed to adapt to the input data stream variations is implemented. This model is used to simulate a CML buffer, where symmetrical and asymmetrical variations in the data stream run-length are considered. The simulation results show that the data run-length variations can degrade the buffer output by as much as 40%.

A universal common-source and common-drain model for 1-20GHz frequency range

Extraction plays an important role in the performance of device models especially in the high frequency regime. The present day extraction techniques mostly use a grounded source or common source (CS) device configuration. The models extracted from the grounded source devices are then used for devices in other configurations in a circuit application. This leads to discrepancies in accurate prediction of the circuit performance. This work investigates, the applicability of the models extracted using CS for other device configurations. It was shown with the help of measured data, in the frequency range of 1-20 GHz, that the models extracted from CS configuration do not predict the performance of a device in common drain (CD) configuration. Based on the above observation, a universal gate impedance model that works for both CS and CD configurations for BSIM3v3 was developed. The gate impedance model was then extended to BSIM4 for both CS and CD configurations. The models for BSIM3v3 and BSIM4 are verified using simulations and compared with the measured data

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S-parameter measurements in silicon. These S-parameter measurements of fully differential positive feedback amplifiers designed in TSMCs 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright

Effect of gate poly-silicon depletion on MOSFET input impedance

One of the most challenging problems encountered in developing RF circuits is accurate prediction of MOS behavior at microwave signal and data frequencies. An attempt is made in this work to accurately model the device input impedance for the 1-20-GHz frequency range. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 0.11-/spl mu/m and 0.18-/spl mu/m technologies. The measured data illustrates that the device input impedance has a nonlinear frequency dependency. It is also shown that this variation in input impedance is a result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region.

Accurate MOS Gate Impedance Model for 200MHz-20GHz Frequency Range

The incessant demand for simultaneous improvements in performance, cost, size and power consumption in the semiconductor industry heavily favors monolithic System-On-Chip (SoC) implementations. Although suffering from inferior device properties compared to other process technologies, CMOS technology offers the unique advantage of high levels of integration of RF, digital and analog circuitry. While faster and smaller transistors are consistently being developed in conformance to Moore’s Law, MOS device modeling has been a major stumbling block in the implementation of these devices [1]. SoC solutions require the coexistence of circuit blocks operating at varied frequencies e.g. RF, analog and digital. The device modeling methodologies for these circuit blocks are radically different. A device in a given technology and dimensions normally is represented by different models based on its frequency of operation. This results in high device characterization costs. Moreover, co-simulation of these models are time consuming due to the introduction of complicated sub-circuits models at RF. Such a simulation environment would benefit hugely from simple, accurate & universally applicable device models. As a first step towards such a model, the MOS gate impedance is modeled for a wide frequency range of 200MHz-20GHz in 0.11μm CMOS technology. To study the input impedance of the MOSFET for the desired frequency range, a large family of NMOS and PMOS devices were fabricated in LSI Logic Corporation’s 0.11μm technology (chip micrograph of a test structure is shown in Fig.1).