Jeff Gelpey

Millisecond Annealing: Past, Present and Future

The challenge of achieving maximal dopant activation with minimal diffusion has re-awakened interest in millisecond-duration annealing processes, almost two decades after the initial research in this field. Millisecond annealing with pulsed flash-lamps or scanned energy beams can create very shallow and abrupt junctions with high concentrations of electrically active carriers, but solutions for volume manufacturing must also meet formidable process control requirements and economic metrics. The repeatability and uniformity of the temperature cycle is the key for viable manufacturing technology, and the lessons from the development of commercial rapid thermal processing (RTP) tools are especially relevant. Advances in the process capability require a fuller understanding of the trade-off between dopant activation, defect annealing. diffusion and deactivation phenomena. There is a strong need for a significant expansion of materials science research into the fundamental physical processes that occur at the short time scales and high temperatures provided by millisecond annealing.

Annealing behavior of clustercarbon™ implants

We report here the use of a novel cluster carbon (C7H7+) implant along with n-type source drain dopant implants (As and P2) to form an embedded Silicon-Carbon (Si:C) layer. The implanted wafers were annealed using millisecond flash anneal (fRTP) followed by a post impulse spike RTP anneal (iRTP) for deactivation studies. The percentage of substitutional carbon ([C]subs) in the formed Si:C layer is characterized by a high-resolution x-ray diffraction (HRXRD) technique. The dependence of post spike anneal temperature on [C]subs show similar behavior for both As and P2 implants. With this clustercarbon implant approach the strain relaxation is only about 10% (90% strain retention) for the post spike anneal temperature of 1000°C. Higher flash anneal temperature leads to lower [C]subs. The sheet resistance is lower in the case of P2 implants when compared to As implants. We present here the detailed characterization of Si:C layer using HRXRD, SIMS, XTEM and activation of n-type dopants using SIMS and Rs measurements.

Implants of ClusterBoron® and ClusterCarbon TM materials for USJ applications - a study with various anneal techniques

We present results for B₁₈H₂₂ implants using ClusterBoron material for PMOS ultra-shallow junction (USJ) applications using solid phase epitaxial regrowth (SPER), high temperature spike anneal, impulse RTP (iRTP) and Flash Assisted RTP^TM anneals. The effect of co-implants on boron activation (Rs) and junction depth (Xj) are compared for both B₁₈SH₂₂ and BF₂ implants. We show that the Rs, Xj parameters obtained for carbon co-implant after spike anneal satisfy the requirements for the 45 nm node technology. With diffusion-less anneals using iRTP at 950°C, we show that B₁₈H₂₂ alone satisfies the 32nm node requirement of Xj at 15nm, but compromises Rs. With flash anneal, Rs and Xj show potential for producing Xj ˜ 15 nm and Rs ≪ 1000 ohms/sq that falls within the requirements for 32nm technology node devices. Additionally for B₁₈H₂₂ -only implants we show TEM images showing no end of range (EOR) damage even after diffusion-less anneals, including SPER anneals.

Leakage Current and Dopant Activation Characterization of SDE/Halo CMOS Junctions with Non‐Contact Junction Photo‐Voltage Metrology

Sheet resistance and leakage current of spike rapid thermal processed (RTP), millisecond flash (fRTP) annealed and chemical vapor deposition (CVD) grown ultra‐shallow junctions (USJ) are compared with a non‐contact junction photovoltage, RsL, technique. Theoretical reverse‐biased diode and non‐contact leakage currents are compared. A significant leakage current increase for spike RTP and fRTP processed USJ formed in halo‐implanted profiles is described by high electron and hole recombination‐generation in the end‐of‐range (EOR) damage layer enhanced by trap assisted and band‐to‐band tunneling. The reduced thermal budget of fRTP allows junction formation with reduced dopant diffusion and with lower sheet resistance. However when strong halo doping is employed, there is often a significant increase in junction leakage relative to that for junctions formed in lightly‐doped test wafers. This increased leakage current can be reduced by annealing the halo implants before implanting the USJ or by lowering the ha...

Optimization Of Si:C Stress Retention And Junction Quality With ClusterCarbon Implantation

ClusterCarbon implantation has been shown to be an effective process for making Si:C stressor layer, particularly due to the self‐amorphization feature of cluster implantation. This work is now extended to show that moderate doses of carbon, producing carbon concentrations near the equilibrium solubility, are very effective at producing stress that is stable with respect to thermal treatments necessary for process integration, including spike anneals, which tend to relax such stress. Further, the carbon incorporation challenges the formation of the NMOS junction structures since both carbon and the dopants compete for silicon lattice sites, and excess carbon causes serious deactivation of the dopant species. Here we show that moderate doses of carbon are critical for the simultaneous achievement of retained stress and low resistance junctions. Multiple carbon implant recipes with various n‐type dopant implants and various annealing conditions, including MSA, spike and combination anneals are shown to achi...

New Approaches for Characterization of Advanced Annealing Techniques for Ultra‐Shallow Junction Formation

Low thermal budget annealing approaches, such as millisecond annealing or solid‐phase epitaxy (SPE), can electrically activate ultra‐shallow junctions (USJ) without excessive diffusion, but they must also remove implant damage to minimize junction leakage. This paper presents results from annealing low‐energy B implants into both crystalline and pre‐amorphized silicon. Some wafers also received As implants for halo‐style doping, and some halo‐implanted wafers were pre‐annealed at 1050 °C before B‐doping. The final anneal was either SPE at 650 °C, spike annealing at 1050 °C, or millisecond annealing with flash‐assisted RTP™ (fRTP™) at temperatures between 1250 °C and 1350 °C. Electrical activation was assessed by sheet resistance (Rs) measurements with conventional four‐point probing (4PP) as well as Hg‐probe 4PP and a non‐contact method. Residual damage was characterized by photoluminescence, thermal wave studies, optical reflectance and non‐contact junction leakage current measurements. Damage from the h...

Flash Annealing Technology for USJ: Modeling and Metrology

Millisecond annealing either by flash lamp or laser appears to be the leading approach to meet the needs of ultra-shallow junction annealing and polysilicon activation for advanced technology nodes. There are many advantages to this technology including high electrical activation, excellent lateral abruptness, controlled and limited dopant diffusion and the ability to engineer the extended defects remaining from the ion implantation. There are also many challenges such as potential pattern effects, local and global wafer stress and difficulty in process integration. Additional challenges include the need to extend the capabilities of process TCAD to allow accurate simulation and prediction of the ms processes. Modeling of diffusion, activation and defect evolution for a variety of technologically interesting doping conditions must be dependable to allow the device designer and process engineer to predict the device behavior after ms annealing. Existing models fall short or still need to be validated. Metrology for ultra-shallow junctions is also a challenge. The ability to accurately and repeatably measure sheet resistance and junction leakage on junctions of the order of 10nm deep is very difficult. This paper provides an overview of flash lamp annealing and deal with some promising extensions of process simulation to enable the predictive modeling of junction behavior under flash lamp annealing conditions. We also examine some of the new metrology techniques for characterization of these very shallow junctions and look at some of the trends exhibited for different junction formation details

Application and advantages of larger Boron cluster ions for 22nm and beyond technology nodes

Cluster Ion implantation offers an attractive alternative approach to realize applications in semiconductor devices at 22nm node and beyond. We present here the advantages of Cluster ions with their special property of creating self-amorphous layer even at a lower dose. Here we show XTEM, SIMS and sheet resistance (Rs) measurements to elucidate the advantages of heavier cluster ion species like B36, B18 and C16. Using millisecond anneal technologies we show here that one can meet ultra-shallow junction depth (Xj) requirements as well as very low sheet resistance values.

Carrier density profiling of ultra-shallow junction layer through corrected C-V plotting

The aim of this report is to present and justify a new approach for carrier density profiling in ultra-shallow junction (USJ) layer. This new approach is based on a capacitance measurement model, which takes series impedance, shunt resistance and the presence of a boron skin on the USJ layer into account. It allows us to extract the depletion layer capacitances in the USJ layer from C-V plotting more accurately and hence to obtain better carrier density profiles. Based on this new approach the carrier density profiles of different USJ layers with and without halo-style implants are obtained and discussed.