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Dive into the research topics where Jeff J. Xu is active.

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Featured researches published by Jeff J. Xu.


international electron devices meeting | 2009

A 25-nm gate-length FinFET transistor module for 32nm node

Chang-Yun Chang; Tsung-Lin Lee; Clement Hsingjen Wann; Li-Shyue Lai; Hung-Ming Chen; Chih-Chieh Yeh; Chih-Sheng Chang; Chia-Cheng Ho; Jyh-Cherng Sheu; Tsz-Mei Kwok; Feng Yuan; Shao-Ming Yu; Chia-Feng Hu; Jeng-Jung Shen; Yi-Hsuan Liu; Chen-Ping Chen; Shin-Chih Chen; Li-Shiun Chen; Leo Chen; Yuan-Hung Chiu; Chu-Yun Fu; Ming-Jie Huang; Yu-Lien Huang; Shih-Ting Hung; Jhon-Jhy Liaw; Hsien-Chin Lin; Hsien-Hsin Lin; Li-te S. Lin; Shyue-Shyh Lin; Yuh-Jier Mii

FinFET is the most promising double-gate transistor architecture [1] to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 µA/µm drive current respectively at 100nA/µm leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with VDD scaling for low power.


international electron devices meeting | 2010

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Chih-Chieh Yeh; Chih-Sheng Chang; Hong-Nien Lin; Wei-Hsiung Tseng; Li-Shyue Lai; Tsu-Hsiu Perng; Tsung-Lin Lee; Chang-Yun Chang; Liang-Gi Yao; Chia-Cheng Chen; Ta-Ming Kuan; Jeff J. Xu; Chia-Cheng Ho; Tzu-Chiang Chen; Shyue-Shyh Lin; Hun-Jan Tao; Min Cao; Chih-Hao Chang; Ting-Chu Ko; Neng-Kuo Chen; Shih-Cheng Chen; Chia-Pin Lin; Hsien-Chin Lin; Ching-Yu Chan; Hung-Ta Lin; Shu-Ting Yang; Jyh-Cheng Sheu; Chu-Yun Fu; Shih-Ting Hung; Feng Yuan

We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications [1–3], can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (ION) improvement and leakage current (IOFF) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), ION of 1325 µA/µm and 1000 µA/µm at 1 nA/µm leakage current under VDD of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.


international electron devices meeting | 2010

A novel multi deposition multi room-temperature annealing technique via Ultraviolet-Ozone to improve high-K/metal (HfZrO/TiN) gate stack integrity for a gate-last process

L. Wu; K.S. Yew; D. S. Ang; Wei Liu; T.T. Le; T.L. Duan; C.H. Hou; X.F. Yu; Di-Hong Lee; K.Y. Hsu; Jeff J. Xu; Hun-Jan Tao; Min Cao; HongYu Yu

ALD HfZrO high-K fabricated by novel multi deposition multi annealing (MDMA) technique at room temperature in Ultraviolet-Ozone (UVO) ambient is systematically investigated for the first time via both physical and electrical characterization. As compared to the reference gate stack treated by conventional rapid thermal annealing (RTA) @ 600°C for 30 s (with PVD TiN electrode), the devices receiving MDMA in UVO demonstrates: 1) more than one order of magnitude leakage reduction without EOT penalty at both room temperature and an elevated temperature of 125°C; 2) much improved stress induced degradation in term of leakage increase and flat band voltage shift (both room temperature and 125°C); 3) enhanced dielectrics break-down strength and time-dependent-dielectric-breakdown (TDDB) life time. The improvement strongly correlates with the cycle number of deposition and annealing (D&A, while keeping the total annealing time and total dielectrics thickness as the same). Scanning tunneling microscopy (STM) and X-ray photoelectron spectroscopy (XPS) analysis suggest both oxygen vacancies (Vo) and grain boundaries suppression in the MDMA treated samples are likely responsible for the device improvement. The novel room temperature UVO annealing is promising for the gate stack technology in a gate last integration scheme.


Archive | 2013

Method of Making a FinFET Device

Huicheng Chang; Jeff J. Xu; Hung-Ta Lin; Chun-Feng Nieh


Archive | 2011

Metal gate stress film for mobility enhancement in FinFET device

Jeff J. Xu; Clement Hsingjen Wann; Chih Chieh Yeh; Chih-Sheng Chang


Archive | 2010

Integrated circuit layout design

Ming-Feng Shieh; Shinn-Sheng Yu; Anthony Yen; Shao-Ming Yu; Chang-Yun Chang; Jeff J. Xu; Clement Hsingjen Wann


Archive | 2008

STORAGE NITRIDE ENCAPSULATION FOR NON-PLANAR SONOS NAND FLASH CHARGE RETENTION

Jeff J. Xu; Chia-Ta Hsieh; Chun-Pei Wu; Chun-Hung Lee


Archive | 2010

Method of forming epi film in substrate trench

Jeff J. Xu


Archive | 2009

Method of pitch halving

Ming-Feng Shieh; Shinn-Sheng Yu; Anthony Yen; Ming-Ching Chang; Jeff J. Xu


Archive | 2010

Method for fabricating a strained structure

Tsung-Lin Lee; Chih-Hao Chang; Chih-Hsin Ko; Feng Yuan; Jeff J. Xu

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