Jeffrey J. Welser

Room temperature operation of a quantum-dot flash memory

A flash-memory device has been fabricated and demonstrated at room temperature by coupling a self-aligned, sub-50-nm quantum dot to the channel of a transistor on a silicon-on-insulator (SOI) substrate. Large threshold voltage shifts of up to 0.75 V are obtained for small erase/write voltages (13 V) at room temperature. At 90 K, evidence of single electron storage is observed. The small size of this device is attractive for achieving high packing densities, while the relatively large output current (100 nA-/spl mu/As), low off-state current (10 pA), and simple fabrication, requiring only minor variations in standard processing, make it suitable for integration with current silicon memory and logic technology.

Electric-field penetration into metals: consequences for high-dielectric-constant capacitors

A consequence of the finite electronic screening length in metals is that electric fields penetrate short distances into the metal surface. Using a simple, semiclassical model of an idealized capacitor, we estimate the capacitance correction due to the distribution of displacement charge in the metal electrodes. We compare our result with experimental data from thin-film high-dielectric-constant capacitors, which are currently leading contenders for use in future high-density memory applications. This intrinsic mechanism contributes to the universally-seen decrease in measured dielectric constant with capacitor film thickness.

A high-speed, high-sensitivity silicon lateral trench photodetector

We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed and high responsivity. The photodetector, fabricated with fully VLSI compatible processes, exhibits a 6-dB bandwidth of 1.5 GHz at 3.0 V and an external quantum efficiency of 68% at 845 nm wavelength. A photoreceiver with a wire-bonded lateral trench detector and a BiCMOS transimpedance amplifier demonstrates excellent operation at 2.5 Gb/s data rate and 845 nm wavelength with only a 3.3 V bias.

Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strain

Summary form only given. Improvements in transport properties through strain have been demonstrated in the operating characteristics of field-effect transistors in the Ga/sub 1-x/In/sub x/As/GaAs and the SiGe/Si system. For CMOS, an improvement in p-channel device characteristics is desirable, and the hole mobility is an appropriate tool for attaining it. Si on relaxed SiGe is one system where such an improvement occurs and has been observed. Here, we discuss how changes in mobility and p-channel device properties can be deliberately made in silicon and silicon-on-insulator (SOI) structures through the introduction of local strain and without a major change in the underlying isolation techniques. Effective mobility changes of up to 40% have been observed for device widths of 1 /spl mu/m in silicon-on-insulator structures.

A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell

This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2/. In the front-end of line (FEOL), the implementation of super-halo design concepts on SOI substrates with a silicon thickness of 45 nm and an ultra-thin heavily nitrided gate dielectric resulted in highest performance devices. The backend of the line (BEOL) for this technology consists of damascene local interconnect followed by up to 10 levels of hierarchical Cu metallization. It utilizes SiLK/spl trade/ low-K dielectric material with a multilayer hard mask stack.

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

High quality ultra-thin TM-SGOI substrate with T/sub SOI/ < 55 nm is developed to combine the device benefits of strained silicon and SOI. 80-90% Id,sat and electron mobility increase are shown in long channel nFET device. For the first time, 20-25% device performance enhancement is demonstrated at 55 nm short channel strained silicon SGOI nFET devices.

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

This work reports on a methodology for achieving high drive current and low gate delay that can be used for the 70 nm technology node. A combination of optimized device design and aggressive gate oxide scaling has been applied to fabricate transistors with saturation currents of 1080 uA/um (NFET, 1171 uA/um dynamic) and 490 uA/um (PFET, 507 uA/um dynamic) at I/sub off/ levels of 100 nA/um for 1.1 volt operation. The physical gate length (L/sub poly/) for these devices is 39 nm. The saturation currents increase to 1180 uA/um and 540 uA/um at I/sub off/ levels of 300 nA/um, which corresponds to gate delays of 0.61 ps and 1.25 ps for NFET and PFET, respectively. These are among the lowest CV/I values ever reported for conventional CMOS scaling. These devices also exhibit excellent high-frequency response, which makes this technology ideally suited for system-on-chip applications that require both high-frequency signal processing and high-speed digital logic. A record high NFET f/sub max/ of 193 GHz has been demonstrated along with an f/sub T/ of 178 GHz.

High speed silicon lateral trench detector on SOI substrate

Lateral trench photodetectors (LTD) on silicon-on-insulator (SOI) have been fabricated using a fully CMOS compatible process. High speed (2.0 GHz), high quantum efficiency (51%), and excellent frequency response characteristics have been achieved at 851 nm with a supply voltage of only 3.3 V.

Emerging Digital Frontiers for Service Innovation

This paper examines emerging digital frontiers for service innovation that a panel discussed at a workshop on this topic held at the 48th Annual Hawaii International Conference on System Sciences (HICSS). The speakers and participants agreed that that service systems are fundamental for service innovation and value creation. In this context, service systems are related to cognitive systems, smart service systems, and cyber-physical systems and depend on the interconnectedness among system components. The speakers and participants regarded humans as the central entity in all service systems. In addition, data, they saw personal data in particular as key to service systems. They also identified several challenges in the areas of cognitive systems, smart service systems, cyberphysical systems, and human-centered service systems. We hope this workshop report helps in some small way to cultivate the emerging service science discipline and to nurture fruitful discussions on service innovation.

Straddle-gate transistor: changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect

Some of the well-recognized constraints in the scaling of the MOSFET are: (a) random-dopants that lead to a large variance in threshold voltage, (b) oxide tunneling that leads to an increase in gate current, and hence strand-by power as well as a reduction in reliability through the increase in carrier flux, (c) limits to the magnitude and shallowness of doping that can be achieved in the source and the drain regions and that lead to poorer sub-threshold swing and higher conductance through electrostatics. The objective of this work is to point out that (a) removal of random dopant effects through removal of channel doping leaves a variance in threshold voltage that is related to lateral fluctuations in the contact region, (b) constant stand-by power density scaling leads to a constraint of 1.5-2.0 nm in oxide thickness for the gate, and (c) the shallow doping regions can be effectively replaced by inversion regions. The straddle-gate transistor, a pentode-like structure, incorporates these ideas together with that of a back-plane structure to achieve an /spl sim/10 nm length scale, where field-effect still dominates, and where the fundamental constraint of source-to-drain tunneling through silicon is restrained by modulating the effective channel length of the device between the on-state and the off-state. At least theoretically, it achieves this length scale within the constraints of power and density, but at the expense of smaller speed improvements with scaling.