Hussein I. Hanafi

A silicon nanocrystals based memory

A new memory structure using threshold shifting from charge stored in nanocrystals of silicon (≊5nm in size) is described. The devices utilize direct tunneling and storage of electrons in the nanocrystals. The limited size and capacitance of the nanocrystals limit the numbers of stored electrons. Coulomb blockade effects may be important in these structures but are not necessary for their operation. The threshold shifts of 0.2–0.4 V with read and write times less than 100’s of a nanosecond at operating voltages below 2.5 V have been obtained experimentally. The retention times are measured in days and weeks, and the structures have been operated in an excess of 109 cycles without degradation in performance. This nanomemory exhibits characteristics necessary for high density and low power.

Fast and long retention-time nano-crystal memory

A threshold-shifting, single transistor memory structure with fast read and write times and long retention time is described. The structure consists of a silicon field-effect transistor with nano-crystals of germanium or silicon placed in the gate oxide in close proximity of the inversion surface. Electron charge is stored in these isolated 2-5 nm size nano-crystals which are separated from each other by greater than 5 nm of SiO/sub 2/ and from the inversion layer of the substrate surface by less than 5 nm of SiO/sub 2/. Direct tunneling of charge from the inversion layer and its storage in the nano-crystal causes a shift in the threshold voltage which is detected via current sensing. The nano-crystals are formed using implantation and annealing or using direct deposition of the distributed floating gate region. Threshold shift of 0.3 V is obtained in Ge-implanted devices with 2 nm of SiO/sub 2/ injection layer by a 4 V write pulse of 300 ns duration. The nano-crystal memories achieve improved programming characteristics as a nonvolatile memory as well as simplicity of the single poly-Si-gate process. The V/sub T/ window is scarcely degraded after greater than 10/sup 9/ write/erase cycles or greater than 10/sup 5/ s retention time. Nano-crystal memories are promising for nonvolatile memory applications.

Single charge and confinement effects in nano‐crystal memories

Use of nano‐crystals of silicon in close proximity (1.5–4.5 nm) of a transistor channel lead to structures with pronounced memory where effects due to discrete number of electrons, confinement‐induced subbands in inversion layers and discrete energy states in quantum dots, random charge distribution in quantum dots, and transmission through a strong barrier are very important. Experimental results show plateaus in threshold voltage at low temperatures, spaced nearly equally apart, and indicative of single electron effects. Varying the oxide thickness shows strong influence on speed and charge retention. We confirm the strength of confinement effects and discuss the underlying considerations in the operation of the memory that are related to the reduced volume, strength of the barrier, and random distribution of the trapped charge in nano‐crystals.

Volatile and non-volatile memories in silicon with nano-crystal storage

A single transistor memory structure, with changes in threshold voltage exceeding /spl ap/0.25 V corresponding to single electron storage in individual nano-crystals, operating in the sub-3 V range, and exhibiting long term to non-volatile charge storage is reported. As a consequence of Coulombic effects, operation at 77 K shows a saturation in threshold voltage in a range of gate voltages with steps in the threshold voltage corresponding to single and multiple electron storage. The plateauing of threshold shift, operation at ultra-low power, low voltages, and single element implementation utilizing current sensing makes this an alternative memory at speeds lower than those of DRAMs and higher than those of E/sup 2/PROMs, but with potential for significantly higher density, lower power, and faster read.

Floating-body concerns for SOI dynamic random access memory (DRAM)

Summary form only given. As operating voltages are reduced it becomes increasingly challenging to write a usable signal into the DRAM storage capacitor because of the nonscalability of threshold voltage, due to the limiting effects of subthreshold slope and substrate sensitivity. Since the maximum wordline voltage is limited by reliability considerations, it is extremely important that the threshold voltage of the DRAM array MOSFET be made as low as possible while meeting the static off-current objective for charge retention. SOI, compared to bulk CMOS, appears attractive for a low-voltage (<2 V) DRAM because its superior subthreshold slope and low substrate sensitivity yield a lower source-follower threshold voltage, resulting in increased logical 1 level to be written for the same operating conditions. However, transient effects of the floating body must be considered when designing for long data retention time and low active power. Although earlier work has considered dynamic retention problems for SOI DRAM during normal read/write operations, simulation results presented in this paper address a transient SOI DRAM leakage mechanism which appears during page mode operation, for both partially and fully depleted designs. Two novel solutions for suppressing the transient leakage mechanism have been investigated.

A model for anomalous short-channel behavior in submicron MOSFETs

Experimental data and simulation results for submicron MOSFETs are reported and used to support a physical explanation for two important anomalies in the dependence of device threshold voltage on channel length. They are the widely observed increase in threshold voltage with decreasing channel length (roll-up), and the more recent observation that the ultimate threshold voltage decrease (roll-off) occurs at a rate which is far in excess of that which can be explained with conventional models of laterally uniform channel doping. A model that attributes roll-up as well as roll-off to lateral redistribution of doping near the source and drain junctions is proposed. This lateral redistribution is caused by crystal defects formed during post-source/drain-implant anneal. The resulting profile consists of an enhancement of background doping adjacent to the junction edge, bounded by a depression of the doping farther into the channel.<<ETX>>

An accurate and simple MOSFET model for computer-aided design

Presents accurate device models (8-10 percent) to describe the drain-current characteristics of short-channel (>1 /spl mu/m) enhancement mode devices (EMD) and ion-implanted depletion-mode devices (DMD). The primary emphasis is on model accuracy and simplicity of formulation. The model form allows efficient extraction of model parameters resulting in accurate description of measured data. Also discussed is a derivation of the model equations with emphasis on a carrier mobility expression which includes the effects of surface scattering, channel scattering, and substrate bias. The effect of intrinsic source and/or drain series resistance on the carrier mobility is also included. The lowering of drain current due to bulk charge in the substrate and current modulation due to short and narrow channel effects and implicitly embedded in the models.

Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance

A CMOS off-chip signal driver that achieves a 2.5-3 times smaller di/dt noise than the conventional design while not incurring the penalty of signal delay is described. It minimizes L di/dt effects by reducing the output signal swing by about a factor of 2 and by providing a controlled ramp rate for the output current. The circuit has a nearly constant output resistance for source termination of transmission lines, and includes a receiver designed for the smaller signal swing. Simulations show a driver-receiver delay of 3 ns for a 7.5-cm line on a multichip package with a peak di/dt of only 12 mA/ns. Driver-receiver delay and noise measurements are also presented. >

Sidewall oxidation of polycrystalline-silicon gate

Evidence is presented demonstrating that sidewall oxidation, a processing step needed for device reliability, can lead to gate oxide thickening in short-channel devices. This increase in thickness is the result of encroachment of birds beaks from the edges of the gate structure into the channel region. The encroachment can be reduced by increasing oxidation temperature and/or using a dry ambient. With a judicious choice of polysilicon sidewall oxidation conditions, minimum gate-to-drain overlap capacitance and adequate device reliability can be achieved.<<ETX>>

A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb*4, 78-mm/sup 2/ chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25 degrees C, and 50-pF load. A 256-b*4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 mu m n-well CMOS process. >