Jeffrey K. Greason

A PLL clock generator with 5 to 110 MHz of lock range for microprocessors

Method for distributing a clock on the silicon backside of an integrated circuit

Latching sense amplifier

PLL clock generator integrated with microprocessor

Memory cell design with vertically stacked crossovers

Method and apparatus for bi-directional bus driver

Method and apparatus for distributing a clock on the silicon backside of an integrated circuit

BiCMOS digital amplifier

Memory test mode for wordline resistive defects

Method for performing a circuit edit through the back side of an integrated circuit die