Jeffrey L. Titus

Single-Event Burnout and Avalanche Characteristics of Power DMOSFETs

Analyses of quasi-stationary avalanche simulations on radiation-hardened power MOSFETs suggest that the single-event burnout (SEB) failure is determined by the devices avalanche characteristics and confirm SEB failure mechanism is due to the turn-on of parasitic bipolar transistor. The heavy ion beam is only acting as a trigger. Simulation results on various 600 V and 250 V radiation-hardened power MOSFETs from International Rectifier are compared to an extensive set of single event effect test results and prove quasi-stationary avalanche simulation is capable of evaluating and predicting SEB susceptibility

An Updated Perspective of Single Event Gate Rupture and Single Event Burnout in Power MOSFETs

Studies over the past 25 years have shown that heavy ions can trigger catastrophic failure modes in power MOSFETs [e.g., single-event gate rupture (SEGR) and single-event burnout (SEB)]. In 1996, two papers were published in a special issue of the IEEE Transaction on Nuclear Science [Johnson, Palau, Dachs, Galloway and Schrimpf, “A Review of the Techniques Used for Modeling Single-Event Effects in Power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 546-560, April. 1996], [Titus and Wheatley, “Experimental Studies of Single-Event Gate Rupture and Burnout in Vertical Power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 533-545, Apr. 1996]. Those two papers continue to provide excellent information and references with regard to SEB and SEGR in vertical planar MOSFETs. This paper provides updated references/information and provides an updated perspective of SEB and SEGR in vertical planar MOSFETs as well as provides references/information to other device types that exhibit SEB and SEGR effects.

Variations in SET pulse shapes in the LM124A and LM111

We present a paper that shows remarkable variation in single-event transient (SET) pulse signal shape for the LM124 operational amplifier, and the LM111 voltage comparator. Both the data and the test methods used are presented.

SEE characterization of vertical DMOSFETs: an updated test protocol

The test protocols for power MOSFETs used in the manufacturers specification sheets are inadequate in that they do not represent a realistic worst-case condition. In addition, the applicable single-event effects (SEE) test methods and guidelines do not provide sufficient details to the user as to what conditions should be used, placing an undue burden on them. This paper addresses several of these deficiencies and others. We present a new test protocol; we suggest a new approach to describe the SEE response; and we provide a model to predict critical ion energies that should produce a worst-case response.

A study of ion energy and its effects upon an SEGR-hardened stripe-cell MOSFET technology [space-based systems]

Experimental observations of an improved single-event gate rupture (SEGR) hardened stripe-cell MOSFET demonstrated that ion beam energy, penetration depth, and strike angle (tilt angle) have a significant influence upon the measured SEGR failure threshold voltage.

Simulation study of single-event gate rupture using radiation-hardened stripe cell power MOSFET structures

A two-dimension simulation study of single-event gate rupture (SEGR) in radiation-hardened stripe cell power MOSFETs is reported. Simulations are performed on stripe-cell structures employing three different neck widths. A simple methodology is presented showing how these simulations can be used to approximate the drain and gate biases required to induce SEGR. These biases are then compared with the experimental data and found to be in good agreement. By means of simulations, we investigated the effects of various physical mechanisms and input parameters, which are likely to be important in SEGR and found that impact ionization plays a crucial role in the process. The simulations show that the N+ source and P+ plug are critical to the hardened design (narrower neck widths). Clearly, simulations could become a useful tool in evaluating certain design and processing variations.

Effect of Buffer Layer on Single-Event Burnout of Power DMOSFETs

It has been shown, both experimentally and theoretically, that the addition of a buffer layer between the epitaxial layer and substrate can improve a devices single event burnout (SEB) survivability. Simulation results show that the choice of buffer, resistivity and thickness, is important in achieving the best device performance (i.e., to fabricate a device capable of withstanding a heavy ion environment under its full rated drain voltage without a significant increase in its on-resistance). Simulation results show that an optimized buffer layer is critical. In other words, if the resistivity is too low or high and/or the thickness is too thick or thin, the drain voltage at which SEB occurs decreases. This paper provides a methodology to select an optimized buffer layer resistivity and thickness.

An improved stripe-cell SEGR hardened power MOSFET technology

A new single-event gate rupture radiation-hardened power MOSFET is reported. It is based upon a well-established radiation-hardened technology described in 1996. The hexagonal cells used in prior work are replaced with a stripe-cell structure producing demonstrated performance improvements.

Experimental evidence of the temperature and angular dependence in SEGR [power MOSFET]

The temperature and angular dependence of Single-Event Gate Rupture (SEGR) experiments, conducted on power DMOS transistors, show that a normal incident angle favors SEGR and elevated temperature is insignificant. Both the oxide and substrate response play a major role in determining the SEGR sensitivity.

Wafer Mapping of Total Dose Failure Thresholds in a Bipolar Recessed Field Oxide Technology

Ionizing radiation failure thresholds were measured across a silicon wafer using 10 KeY x-rays to determine the success of hardened process modifications and to examine wafer level hardness assurance screening techniques. Topological wafer maps of the total dose failure response for Signetics 74F00 circuits are presented.