Sandra Liu

Single-Event Burnout and Avalanche Characteristics of Power DMOSFETs

Analyses of quasi-stationary avalanche simulations on radiation-hardened power MOSFETs suggest that the single-event burnout (SEB) failure is determined by the devices avalanche characteristics and confirm SEB failure mechanism is due to the turn-on of parasitic bipolar transistor. The heavy ion beam is only acting as a trigger. Simulation results on various 600 V and 250 V radiation-hardened power MOSFETs from International Rectifier are compared to an extensive set of single event effect test results and prove quasi-stationary avalanche simulation is capable of evaluating and predicting SEB susceptibility

Effect of Buffer Layer on Single-Event Burnout of Power DMOSFETs

It has been shown, both experimentally and theoretically, that the addition of a buffer layer between the epitaxial layer and substrate can improve a devices single event burnout (SEB) survivability. Simulation results show that the choice of buffer, resistivity and thickness, is important in achieving the best device performance (i.e., to fabricate a device capable of withstanding a heavy ion environment under its full rated drain voltage without a significant increase in its on-resistance). Simulation results show that an optimized buffer layer is critical. In other words, if the resistivity is too low or high and/or the thickness is too thick or thin, the drain voltage at which SEB occurs decreases. This paper provides a methodology to select an optimized buffer layer resistivity and thickness.

Effects of Ion Species on SEB Failure Voltage of Power DMOSFET

This paper presents and explains test results showing the effect of ion species on the single event burnout (SEB) failure voltage using a SEB sensitive engineering power double diffused metal oxide silicon field effect transistor (DMOSFET). The analyses show the determining factor of tested SEB failure voltage is the ion species itself rather than test or beam conditions such as initial beam energy, surface linear energy transfer (LET), ion range, or ionized charge. Also, results from five test facilities and five test setups are compared to determine if there will be differences in test results when different test setups or different heavy ion accelerator facilities were used.

Effects of Ion Atomic Number on Single-Event Gate Rupture (SEGR) Susceptibility of Power MOSFETs

The relative importance of heavy-ion interaction with the oxide, charge ionized in the epilayer, and charge ionized in the drain substrate, on the bias for SEGR failure in vertical power MOSFETs is experimentally investigated. The results indicate that both the charge ionized in the epilayer and the ion atomic number are important parameters of SEGR failure. Implications on SEGR hardness assurance are discussed.

Evaluation of Worst-Case Test Conditions for SEE on Power DMOSFETs

Extensive single event effects tests were performed on a new generation, the R6 process, of radiation-hardened 600-volt and 250-volt power metal-oxide semiconductor field-effect transistors (MOSFETs) from international rectifier using two different ions (krypton and xenon) at many different beam energies, Bragg peak positions, and drain and gate biases. Results show that there is no worst-case test condition for single event burnout but positioning of the energy deposition is critical for single event gate rupture

Worst-Case Test Conditions of SEGR for Power DMOSFETs

Heavy ion test results show worst-case test conditions for single-event gate rupture (SEGR) of power MOSFETs. Contrary to common belief, the worst-case ion condition for SEGR is not the ion with the deepest penetration depth in the device or highest LET at the die surface, but the ion beams with Bragg peak positioned at or near the interface of the epitaxial layer and the highly doped substrate. The factors that have significant impact on SEGR thresholds are evaluated and discussed. The factors that are considered include: ion beam, drain bias, gate bias, ion species, ion range, surface LET and the construction layer of the power DMOSFET. An estimated worst-case ion range table for krypton, xenon and gold is provided for reference.

Analysis of Commercial Trench Power MOSFETs' Responses to

This paper presents a detailed analysis of commercial trench power MOSFET responses to Co60 irradiation of all key d.c. electrical test parameters. Charge trapping in the gate oxide causes the threshold voltage (V TH) to shift, which, in turn, accounts for most of the degradation exhibited by the device after irradiation.

{\rm Co}^{60}

This paper evaluates protective single event burnout test method on power DMOSFETs to confirm that it provides accurate test results as the destructive test method when performed properly. The selection of resistor values, protective mechanism, and considerations in calculating SEB cross-section are discussed.