Chao-Jen Huang

The solder on rubber (SOR) interconnection design and its reliability assessment based on shear strength test and finite element analysis

A novel chip-on-metal structure of the advanced wafer level chip scale package (WLCSP) which has the capability of redistributing the electrical circuit is proposed in this study. In the WLCSP, the solder on rubber (SOR) design expands the chip area and also provides a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. By using the solder ball shear test, the stress/strain-released behavior in the SOR structure is investigated in this research. On the other hand, a three-dimensional nonlinear finite element (FE) model for the ball shear test is established to assist the design of the package. The force-displacement curves from the FE analysis are compared with the experimental results to demonstrate the accuracy of the simulation. Likewise, the issue from element mesh density is also discussed herein. The investigation reveals that the SOR structure could highly decrease the damage in solder bumps from the ball shear test. Furthermore, the transferred stress/strain in the interconnect near the contact pad could be diminished through a suitable layout of redistribution lines.

Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability

In this study, a wafer level chip scaled packaging (WLCSP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the fan-out WLCSP, the solder bumps could be located on both the filler polymer and chip surface. The concept of the fan-out WLCSP and the processes of fabricating the novel fan-out WLCSP would be described. In addition, the reliability characteristic of the fan-out WLCSP in packaging level is described by using the two-dimensional finite element model. The 25 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging

Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test

Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.

Reliability and parametric study on chip scale package under board-level drop test

The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of displacement, and the vibration frequency is lower than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude. Several parametric studies including discussions on the chip thickness, chip size, dielectric layer thickness and hardness, and the solder ball distribution were performed to improve reliability.

Failure Mode and Thermal Performance Analysis of Stacked Panel Level Package (PLP)

In this paper, a new packaging technology, chip-on-metal (COM) panel level package (PLP), with stacking and fan-out capabilities is proposed. Moreover, the concept of the COM PLP and the process of its fabrication are described. During the manufacturing process, the trench around the chip is filled with the filler polymer material. Therefore, the solder bumps could be located on both the filler polymer and the chip surfaces by the redistribution lines, and the pitch of the chip side is fanned-out. In our previous research, it was shown that the physical behavior of the COM PLP is different from that of the conventional wafer level package (WLP). To assess the thermal performance and thermo-mechanical characteristic of the proposed PLP, the finite element analysis (FEA) in board level is carried out. The junction temperature and thermal resistance of the COM PLP and the stacked PLP are discussed to study the thermal performance. At the same time, the mean cycle to failure of the solder joints is predicted, and the result shows that the reliability of solder joints can be highly improved by the proposed packaging technology. However, the new failure mode may occur at the metallic traces so the reliability assessment of the signal trace is also investigated. In addition, the parametric analysis of the COM PLP is studied to enhance the thermal performance and reliability characteristic. Thus, the PLP technology will have high potential for various applications in the near future.Copyright

Determination of mechanical property of nanostructure using nano-macro equivalent mechanics method

The importance of research in nanoscale structure grew in the last two decades. However, the experimental method in this research field is not yet sufficiently advanced to provide people with a reliable and suitable mechanical property. The aim of this paper was to determine the utility of the equivalent method for establishing a mechanical property definition. In this method, equivalent atomistic-continuum elements replaced an originally discrete atomic structure. The method was based on the semi-empirical potential function and the finite element method. This study utilized a spring network model to describe interaction force of bi-atoms, and to investigate the Youngs modulus of silicon/germanium, carbon nanotube, and copper in a nanostructure. The Youngs moduli of these materials were confirmed by literature. Results indicated that the equivalent mechanics method may provide the basis for a useful and convenient process.

Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies

In this study, the thermo-mechanical finite element (FE) analysis of the 3D chip stacking packaging is accomplished by employing the commercial software, ANSYS®. After manufacturing process, the thickness of the deposited material becomes variable. For the most part, this is due to the uncertainty of the manufacture process. In analyzing the effect of thickness difference, the process modeling technique is adopted. The technique can be demonstrated by comparing simulation results and the designed experiment for established chip displacement measurements. The out-of-plane displacement of the fabricated chip is measured by the Twyman-Green (T/G) interferometer. According to the results simulated by the validated process modeling technique, the effect of the thickness difference of the ABF layer is insignificant. In thermo-mechanical FE analysis, the thermal expansion of ABF material can induce stress concentration at the copper via. Moreover, thermal expansion of the ABF material and copper via can also affect the reliability of the silicon chip. Based on the design concept, the effect of the copper via diameter is analyzed. Based on the results, the stress concentration phenomenon at the copper via improves as the diameter increases. However, a larger thermal expansion of the copper via can damage the chip structure because of the larger diameter.Copyright