Yo-Hao Tu

A low jitter delay-locked-loop applied for DDR4

This work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the de-velopment and breakthrough of the CMOS process technology. The complexity of design and frequency of clock in memory has also been rapidly increasing. Thus, the reliability of synchronous circuits becomes more and more essential. Dynamic Random Access Memory (DRAM) has progressed to DDR4, reaches data rate 1.6 Gbps - 3.2 Gbps. The stability of clock becomes an essential part of design. This work presents a technique that includes a current-matching charge pump and an on-chip supply regulator in the delay-locked loop (DLL). The design is implemented by TSMC CMOS 1P/9M 90 nm technology with a nominal supply voltage 1.2 V and I/O supply voltage 2.5 V. The input frequency is at 1.6 GHz. Peak to peak jitter is 12.33 ps and RMS jitter is 1.66 ps. The power dissipation of DLL is 15.6 mW and chip area is 0.047 mm2.

A chaotically injected timing technique for ring-based oscillators

This work proposes a chaotically injected timing technique (CITT) for ring-based oscillators. The quality of clock signal affects the normal motion of the entire circuit. In many oscillators and clock generators show the performance comparison through jitters and phase noise. The injection-locked ring-based oscillators have advantages of jitters, phase noise and area cost. However, there is a contingent effect, injected spur. By adopting the CITT, the injected phase pattern can be randomized and break the periodicity of injected signal to solve the high injected spur effect. The CITT can reduce the level of phase noise by 29 dB compared to the free-run oscillator. The experiment chip of the proposed CITT is implemented by 90 nm CMOS process. The measured output frequency is 5 GHz at supply voltage of 1 V. The level of phase noise is -99 dBc at frequency offset of 1 MHz under injected frequency of 1 GHz.

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6GHz at 0.6V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1mW at 1.6GHz and 0.036mm2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.

A low supply voltage synchronous mirror delay with quadrature phase output

This work proposes a low supply voltage synchronous mirror delay (SMD) circuit with quadrature phase output in intra-chip. In some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, for some specific applications, the circuits need to operate in a low supply voltage environment. In some communication systems, they even need to have I/Q clock signals. Therefore, this is often led to a synchronous circuit with extra functional capabilities. The proposed SMD with the quadrature delay path can operate in the low supply voltage environment by using the low-voltage techniques. The chip is implemented by TSMC CMOS 1P/9M 90 nm technology with a low supply voltage, 0.5 V. The operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and 3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The core area is 188 × 171 um2.

Low supply voltage and multiphase all-digital crystal-less clock generator

A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from - 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and - 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm 2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.

A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering

A body sensor node system-on-chip (SoC) is designed and implemented. The SoC integrates analog front end (AFE), a high-resolution analog-to-digital converter (ADC), an RF-to-DC rectifier, a low dropout (LDO) regulator, and a digital signal processing (DSP) block. The batteryless SoC is powered by RF of 2.45GHz. The rectifier generates 1.8V output and the LDO converts the voltage to stable 1.6V supply for AFE, ADC, and DSP blocks. A pseudo-resistor with huge resistance is used in AFE to support tunable low cut-off frequency and to facilitate compact SoC integration. The DSP can be set to deliver raw data, wavelet-domain data, and compressed-sensing (CS) data. The entire SoC is 1.7×2.5 mm2 and can support invasive/non-invasive health-monitoring with low power consumption.

A Synchronous Mirror Delay with Duty-Cycle Tunable Technology

This study presents a synchronous mirror delay (SMD) with duty-cycle tunable technology. For some specific applications, the duty cycle of clock signals have to be varied or calibrated. By tuning the duty cycle, the proposed SMD is desirable to be used for the relative clock synchronous circuits in the system-on-chip (SoC) systems, micro-processors and double-data-rate memory applications. It can not only calibrate the variations of duty cycle but also offer an extra functional capability for some specific applications. The proposed SMD is implemented by TSMC 1P/9M 90 nm CMOS technology with a normal supply voltage, 1.2 V. It can generate the output clock with the duty cycle of 30% to 70% in steps of 10%. The operating rang is from 0.8 GHz to 1.6 GHz. The total power consumption is around 18 mW at 1.6 GHz and the core area occupies 0.370 mm x 0.205 mm.

A 3 GHz DLL-based clock generator with stuck locking protection

This study presents a 3-GHz DLL-based clock generator with stuck locking protection. In this paper, a proposed duty cycle corrector solves the problem of the sensitivity to half transparent (HT) architecture and the stuck locking error in the DLL simultaneously. Based on the frequency-multiplied technique, the multiphase DLL architecture synthesizes a 3-GHz output clock. The post-layout simulation results are based on TSMC 0.18 µm 1P6M CMOS process. The proposed architecture locks into the input frequency of 250 MHz. Operating at the 3-GHz frequency multiplier output, the simulated peak-to-peak jitter is 2.94 ps and 31.17 ps for the 250-MHz locked frequency and 3-GHz synthesized frequency, respectively. The chip area is less than 0.745 × 0.745 mm2 and the power consumption is 20.9 mW at a supply of 1.8 V.