Jens Poppe

Stress migration model for Cu interconnect reliability analysis

Stress migration (SM) reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative SM analysis and lifetime estimates for products were not available due to lack of a suitable SM model. In this paper, we establish a comprehensive SM model for quantitative stress-induced-voiding (SIV) risk analysis for 32 nm technology and beyond. It was found that the SIV risk is dependent on both stress temperatures and geometric structural line widths as driving forces. Based on the new SM model, the SM lifetime can be estimated from measurable SM data and accelerated SM test methods can be designed to meet the qualification criteria.

Stress-induced-voiding risk factor and stress migration model for Cu interconnect reliability

SM reliability data have been treated qualitatively to define pass or fail criteria in the past. However, realistic quantitative stress-induced-voiding (SIV) risk analysis and lifetime estimates for products were not available due to lack of quantitative data and a suitable SM model. In this paper, we provide quantitative analysis of SIV risk based on geometry factors and further establish a comprehensive SM model for SM lifetime estimation for 32nm technology and beyond. An SIV risk factor is defined to quantify the relative risks of Cu BEOL interconnect structures. Based on the new SM model, an effective geometry factor was found for an accelerated SM test method to perform SM lifetime estimation from measurable SM data.

An experimental methodology for the in-situ observation of the time-dependent dielectric breakdown mechanism in Copper/low-k on-chip interconnect structures

This study captures the time-dependent dielectric breakdown kinetics in nanoscale Cu/low-k interconnect structures, applying in-situ transmission electron microscopy (TEM) imaging and post-mortem electron spectroscopic imaging (ESI). A “tip-to-tip” test structure and an experimental methodology were established to observe the localized damage mechanisms under a constant voltage stress as a function of time. In an interconnect structure with partly breached barriers, in-situ TEM imaging shows Cu nanoparticle formation, agglomeration and movement in porous organosilicate glasses. In a flawless interconnect structure, in-situ TEM imaging and ESI mapping show close to no evidence of Cu diffusion in the TDDB process. From the ESI mapping, only a narrow Cu trace is found at the SiCN/OSG interface. In both cases, when barriers are breached or still intact, the initial damage is observed at the top interface of M1 between SiCN and OSG.

Backend-of-line reliability improvement options for 28nm node technologies and beyond

This paper reviews the most encouraging process options for improving backend-of-line reliability performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Furthermore, time-dependent dielectric breakdown has to be carefully evaluated. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28nm technology nodes. In addition to electromigration and time-dependent dielectric breakdown, the impact of the various process options on stress migration performance is discussed.

Comparison of Process Options for Improving Backend-of-Line Reliability in 28 nm Node Technologies and Beyond

This paper compares the most encouraging process options for improving electromigration performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28 nm technology nodes. In addition, the impact of the various process options on stressmigration and time-dependent dielectric breakdown are discussed.

New failure mechanism during high temperature storage testing and its application on SIV risk evaluation

In this paper we showed results on high temperature storage tests performed on 90nm, 65nm and 45nm node material with different back end of line stacks. We have seen a strong impact of BEOL stack up on resistance traces of tests at temperature of over 250°C for 1000h. We found that the detected resistance increases are not related to stress migration phenomena but to changes in barrier integrity. The results suggest that the barrier is oxidizing due to oxygen supplied by the SiCOH ILD. First look into future technologies by adopted barrier processes simulating corresponding barrier thicknesses we see an acceleration of this results. Porous SiCOH which is used as baseline material for 45nm an beyond is even pronouncing this effect. This is definitely showing that this effect might become severe in future technologies.

Investigation Of Stress‐Induced Voiding Of Double Cross‐Shaped Single Via Test Structure And Derivatives For Deep‐Sub Micron Technology Nodes

We have conducted stress migration experiments with specifically designed cross‐, T‐ and L‐shaped single via test structures with wing variations for stress‐induced voiding risk studies. The designed test structures were investigated under design rule compliant line widths at 45 nm and 32 nm technology nodes. The preliminary results of our study have shown the general trend of stress‐induced voiding risk factor for a single via is scalable to the number of wings and their configurations. We discussed these findings in terms of active diffusion model, grain distribution and “unhappy landing” model assumptions. With this approach we will be able to correlate the stress‐induced voiding risk for different geometrical and dimensional designs.

Stress Phenomena In Times Of Porous Low‐k Dielectrics

Since the introduction of copper as an interconnect material into the Back End of Line (BEoL) stack approximately ten years ago, the biggest challenge for reducing the RC values is the reduction of the k‐value of the dielectric. Significant reduction can only be reached by the introduction of new ILD material. These new materials are very challenging with respect to all investigated BEoL reliability phenomena such as electromigration (EM), stress migration (SM) and time dependent dielectric breakdown (TDDB).In this paper we are going to give an overview over the reliability robustness challenges due to the introduction of porous dielectrics. Besides these general aspects we accentuate on how the general SM performance suffers from the introduction of the new material. Within this particular context we will show possible solutions for stress migration margin losses. It was not obvious before that the introduction of electromigration improvement options such as surface silicidation or metal capping of the c...