Jeong-Hee Chung

A robust alternative for the DRAM capacitor of 50 nm generation

As a new alternative for the DRAM capacitor of 50 nm generation, Ru/Insulator/TiN (RIT) capacitor with the lowest Toxeq of 0.85 nm has been successfully developed for the first time. TiO/sub 2//HfO/sub 2/ and Ta/sub 2/O/sub 5//HfO/sub 2/ double-layers were used as dielectric materials. After full integration into 512 Mbits DRAM device, the RIT capacitor showed good electrical properties and thermal stability up to 550/spl deg/C and its time-dependent-dielectric-breakdown behavior sufficiently satisfied 10-year lifetime within a DRAM operation voltage.

TiN/HfO/sub 2//TiN capacitor technology applicable to 70 nm generation DRAMs

We have developed a cylindrical TiN/HfO/sub 2//TiN (TIT) capacitor for 70 nm DRAMs application. TIT capacitors with HfO/sub 2/ films deposited by ALD(Atomic Layer Deposition) using Hf(NEtMe)/sub 4/ precursor and O/sub 2/ plasma as a reactant is shown to be applicable to DRAM device below 70 nm design rule for the first time. It shows the thermal budget endurance against back-end process of DRAM device as well as the very low enough Toxeq of about 13 /spl Aring/ to provide the sufficient cell capacitance.

New approaches to improve the endurance of TiN/HfO/sub 2//TiN capacitor during the back-end process for 70nm DRAM device

We have successfully developed a MIM capacitor process technology with a HfO/sub 2/ single layer deposited by ALD (atomic layer deposition), where a Hf(NEtMe)4 and CVD-TiN cylinder-type storage-node were used as a Hf liquid source and bottom electrode for 90 nm-scale DRAMs. Our experimental results indicated that NH/sub 3/-plasma treatment on HfO/sub 2/ film promoted crystallization below 400/spl deg/C as well as the formation of a HfO/sub x/N/sub y/ layer on the surface of the HfO/sub 2/ film. With this treatment, it was possible to solve the degradation problem of the leakage current depending on deposition method of the top electrode, and a stable leakage current without degradation was obtained up to 550/spl deg/C. As a result, a TiN/HfO/sub 2//TiN (TIT) capacitor with 1.4 /spl mu/m-height storage node was successfully demonstrated with stable leakage current of 1fA/cell at +1.2 V and high cell capacitance of 40 fF after metal-2 integration.

Evaluation of Novel Sr Precursors for Atomic Layer Deposition of SrO Thin Film

Atomic layer deposition (ALD) process to deposit SrO film using novel Sr precursor – Sr (Methoxy-TetramethylHeptadiene)2 was estimated. Fig.1 showed the chemical structure of the synthesized Sr(MTHD)2. Fig. 2 showed thermal gravimetric analysis results of Sr(MTHD)2 and commercially used Sr (Tetra-Methyl Hetadiene)2. 50 % precursor evaporation temperature (T50) of Sr (MTHD)2 was 330 C, which was 30 C lower than that of Sr(TMHD)2. Liquid delivery system with flash evaporator was used to transport the precursors to substrate. The precursors were dissolved in Tetra Hydro Furan (THF) to prevent clogging during the delivery process. Ozone was used as a reactant to deposit SrO. It was found that thickness uniformity range of SrO film on Si wafer was less than 2 %. The deposition rate of SrO film using new Sr precursor was 0.4 A/cycle, which was almost same regardless of substrate temperatures up to 400 C. High vapor pressure and good thermal stability of new Sr precursor make it promising candidates for ALD precursors to deposit SrTiO3, aSrTiO3. Fig.1. Chemical structure of Sr(MTHD)2

Ru/TiO2/ZrO2/TiN (RIT-TiO2/ZrO2) Capacitor Structure for the 50nm DRAM Device and beyond

Advanced Process Development Team, *Process Development Team, Semiconductor R&D Division, Samsung Electronics Co., Ltd. San#24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea 449-711 E-mail: soon310.lim@samsung.com Introduction As the innovative scale-down of DRAM device continues, 50nm generation becomes close at hand. As shown in Fig. 1, to satisfy the cell capacitance of 25fF with 1.7μm storage-node height in 50nm design rule, the equivalent oxide thickness (Toxeq.) of a dielectric material should be as low as 0.8nm. TiN/HfO2/TiN (TIT) capacitor has been successfully developed for 70nm generation [1], but it seems to be difficult to meet the requirements for sub-60nm device. When Ta2O5 or TiO2 was implemented as the dielectric of the TIT capacitor to reduce Toxeq. below 1.2nm, it was difficult to suppress the leakage current because of low barrier height and poor interface between TiN and high-k dielectric (Figure 2). On the other hand, Ru/Insulator/Ru (RIR) capacitor using high-k dielectrics has some problems yet to be solved, such as the contact-plug oxidation and Ru electrode agglomeration during the back-end process. In the previous study [2], we have proposed Ru(top)/Insulator/TiN(bottom) capacitor as an alternative for the DRAM capacitor below 50nm generation. The leakage currents of Ta2O5 and TiO2 could be reduced by the application of Ru top electrode. And also a reliable storage-node was obtained with solid TiN bottom electrode. RIT-Ta2O5/HfO2 was successfully developed corresponding to Toxeq. 1.1nm with 1fA/cell leakage current after full integration. In this study, to reduce Toxeq. value lower than 0.8nm, we have introduced ZrO2 as dielectric layers. We have compared and discussed the electrical characteristics of RIT-TiO2/ZrO2 and RIT-TiO2/HfO2 capacitors. The electrical properties after back-end metal-line integration and time-dependent-dielectricbreakdown behavior were also investigated .

Formation of sub-100 nm contact hole patterns using a novel resist material

Flow process using a novel resist called the SMART (Samsung Advanced Resist for Thermal flow process) was studied. The SMART consisted of conventional polyhydroxy styrene-based polymers and the additives for cross-linking reactions with base polymers. When the SMART was used, 240 nm contact hole patterns were reduced to 90 nm final patterns without much pattern deformation. At 90 nm resolution, the critical dimension (CD) uniformity on 200 mm wafer was less than 20 nm. The etching selectivity of resist to silicon oxide was increased due to the cross-linking reaction. Based on these results, the flow process by the SMART is a very promising candidate for the fabrication of gigabit devices.