Jeong-Hwan Yang
Samsung
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Jeong-Hwan Yang.
international reliability physics symposium | 2004
Shigenobu Maeda; Jung-A Choi; Jeong-Hwan Yang; You-Seung Jin; Su-Kon Bae; Young-Wug Kim; Kwang-Pyuk Suh
Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The <100>-direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.
symposium on vlsi technology | 2004
Shigenobu Maeda; You-Seung Jin; Jung-A Choi; Sun-Young Oh; Hyun-Woo Lee; Jae-yoon Yoo; Min-Chul Sun; Ja-hum Ku; Kwon Lee; Su-Gou Bae; S. K. Kang; Jeong-Hwan Yang; Young-Wug Kim; Kwang-Pyuk Suh
Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.
international electron devices meeting | 2003
Jeong-Hwan Yang; You-Seung Jin; Hyae-ryoung Lee; Kyoung-Seok Rha; Jung-A Choi; Su-Kon Bae; Shigenobu Maeda; Young-Wug Kim; Kwang-Pyuk Suh
Fully working 1.25 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology. This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported.
international conference on vlsi and cad | 1999
Jeong-Hwan Yang; Dae-Rim Kang; Seong-Ho Kwak; Su-Cheol Lee; Young-Wug Kim; Kwang Pyuk Suh
The characteristics of 20 /spl Aring/ gate oxide formed by an RTO (Rapid Thermal Oxidation) process with an NO+O/sub 2/ mixture ambient have been investigated. Due to the high nitrogen concentration in the oxide, good boron penetration suppression and higher interface trap density were observed. The low thermal cycle of the RTO process facilitated the formation of SSR (Super Steep Retrograde) channel and reduced RSCE (Reverse Short Channel Effect). The transistor performance was Idsat n/p=925/370 /spl mu/A//spl mu/m for Vdd=1.5 V and Idoff n/p=10 nA//spl mu/m. The TDDB and hot carrier characteristics were evaluated and found to be satisfactory.
Archive | 2003
Jeong-Hwan Yang; Young-Wug Kim
Archive | 2001
Jeong-Hwan Yang; Young-Wug Kim
Archive | 2005
Shigenobu Maeda; Jeong-Hwan Yang; 茂伸 前田; 正煥 梁
Archive | 2010
Shigenobu Maeda; Jeong-Hwan Yang
Archive | 2008
Shigenobu Maeda; Jeong-Hwan Yang
Archive | 2004
Jin-Young Kim; Maeda Shigenobu; Chang-jin Kang; Jeong-Hwan Yang