Jeong-Hwan Yang

Negative bias temperature instability in triple gate transistors

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The <100>-direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.

Impact of mechanical stress engineering on flicker noise characteristics

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

Fully working 1.25 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology. This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported.

Device characteristics and reliability for 0.18 /spl mu/m MOSFET with 20 /spl Aring/ gate oxide formed by RTO

The characteristics of 20 /spl Aring/ gate oxide formed by an RTO (Rapid Thermal Oxidation) process with an NO+O/sub 2/ mixture ambient have been investigated. Due to the high nitrogen concentration in the oxide, good boron penetration suppression and higher interface trap density were observed. The low thermal cycle of the RTO process facilitated the formation of SSR (Super Steep Retrograde) channel and reduced RSCE (Reverse Short Channel Effect). The transistor performance was Idsat n/p=925/370 /spl mu/A//spl mu/m for Vdd=1.5 V and Idoff n/p=10 nA//spl mu/m. The TDDB and hot carrier characteristics were evaluated and found to be satisfactory.