Young-Wug Kim

Negative bias temperature instability in triple gate transistors

Negative bias temperature instability (NBTI) in triple gate transistors was investigated for the first time. It is found that the threshold voltage shift caused by negative bias temperature stress in conventional configuration of triple gate transistors is worse than that in planar transistors. This is due to the larger trap state density of the [110] side surface of the active silicon and it is verified by comparing two types of triple gate transistors each of which has [110] side surface and (100) side surface. The <100>-direction channel is proposed as one of the structural options to reduce the degradation of NBTI in triple gate transistors.

Thermal stability of atomic-layer-deposited HfO2 thin films on the SiNx-passivated Si substrate

HfO2 thin films were deposited on SiNx-passivated Si wafers at 300 and 400 °C using an atomic-layer-deposition technique. The SiNx films were deposited by another atomic-layer-deposition process at 595 °C. The SiNx films worked well as barriers to both Si and O diffusion, resulting in a small decrease in the capacitance density even after post-annealing at temperatures up to 1000 °C, compared either to the HfO2 film deposited directly on Si or an Al2O3-barrier-layer/Si substrate. The decrease in the capacitance density after post-annealing, although relatively small, was due to Hf and O diffusion into the interface layer. Interestingly, post-annealing under an atmosphere containing small amount of oxygen (∼1%) decreased the capacitance density to a smaller degree. However, the interface and bulk capturing of the carrier was serious, resulting in a rather large hysteresis (∼100 mV) voltage in the capacitance–voltage measurements even after post-annealing.

Impact of mechanical stress engineering on flicker noise characteristics

Relationship between mechanical stress engineering and flicker noise are clarified for the first time using a 50nm level CMOS technology. It is found that enhanced mechanical stress degrades flicker noise characteristics. Trap states and dipoles generated by the stress are considered to be the cause of degradation. The transistor performance enhancement with flicker noise reduction by nitrogen profile optimization in gate dielectric is demonstrated as a countermeasure.

Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO/sub 2//Si interface. We have achieved a significant lifetime improvement (90/spl times/) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.

Improved current performance of CMOSFETs with nitrogen incorporated HfO 2 -Al 2 O 3 laminate gate dielectric

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

The effect of body contact arrangement on thin SOI MOSFET characteristics

Abstract Several body contact arrangement types have been studied to improve the parasitic phenomena such as the edge transistor effect and the bipolar action. The H-gate SOI MOSFET with the body contacts at both ends of channel was found to be most effective to suppress the edge transistor effect and reduce the drain leakage current and the bipolar action.

Ultrathin gate oxide grown on nitrogen-implanted silicon for deep submicron CMOS transistors

Nitrogen implantation on the silicon substrate was performed before the gate oxidation at a fixed energy of 30 keV and with the split dose of 1.0/spl times/10/sup 14//cm/sup 2/ and 2.0/spl times/10/sup 14//cm/sup 2/. Initial O/sub 2/ injection method was applied for gate oxidation. The method is composed of an O/sub 2/ injection/N/sub 2/ anneal/main oxidation, and the control process is composed of a N/sub 2/ anneal/main oxidation. CMOS transistors with gate oxide thickness of 2 nm and channel length of 0.13 /spl mu/m have been fabricated by use of the method. Compared to the control process, the initial O/sub 2/ injection process increases the amount of nitrogen piled up at the Si/SiO/sub 2/ interface and suppresses the growth of gate oxide effectively. Using this method, the oxidation retarding effect of nitrogen was enhanced. Driving currents, hot carrier reliability, and time-zero dielectric breakdown (TZDB) characteristics were improved.

A novel Al-reflow process using surface modification by the ECR plasma treatment and its application to the 256 Mbit DRAM

A novel Al-reflow process with the electron cyclotron resonance (ECR) plasma treatment for the modification of underlayers was developed in a vacuum isolated sputtering equipment. The key feature of this technology is the introduction of the in-situ ECR plasma treatment for the modification of the surface characteristics such as surface morphology and stoichiometry of the TiN wetting/barrier layer. High wettability of the Al film was obtained on the ECR-treated TiN surface, producing a conformal Al film on the sidewall of the contact hole before the reflow process. Consequently, complete filling of contact holes with Al was achieved in deep sub-micron contact holes with a high aspect ratio. This study has demonstrated that the Al-reflow process can be extended to the process of the devices of 256 Mbit DRAM generation and beyond.<<ETX>>

SET/CMOS hybrid process and multiband filtering circuits

We have developed an integration technology for the single electron transistor (SET)/CMOS hybrid systems. SET and CMOS transistors can be optimized without any possible degradation due to mixing dissimilar devices by adopting just one extra mask step for the separate gate oxidation (SGOX). We have confirmed that discrete devices show ideal characteristics required for the SET/CMOS hybrid systems. An SET shows obvious Coulomb oscillations with a 200-mV period and CMOS transistors show high voltage gain. Based on the hybrid process, new hybrid circuits, called periodic multiband filters, are proposed and successfully implemented. The new filter is designed to perform a filtering operation according to the periodic multiple blocking bands of which a period is originated from the SET. Such a novel function was implemented efficiently with a few transistors by making full use of the periodic nature of SET characteristics.

Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors

Fully working 1.25 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology. This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported.