Jeong-Mo Hwang

Stacking sequence design of composite laminates for maximum strength using genetic algorithms

Abstract This paper uses genetic algorithms (GAs) for the optimal design of symmetric composite laminates subject to various loading and boundary conditions. To analyze these laminates, the finite element method based on shear deformation theory is used. The Tsai–Hill failure criterion is taken as the fitness function, and the ply orientation angles are the design variables. In the GA, tournament selection and the uniform crossover method are used. The elitist model is also used for an effective evolution strategy and the creeping random search method is adopted in order to approach the solution with high accuracy. Optimization results are given for various loading and boundary conditions. The results show that optimization via a GA can find the global optimal solution leading to a substantial decrease in the failure index.

Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's

A real, peripheral and corner leakage current densities are extracted from measured data of area, perimeter and corner intensive p/sup +/-n junctions fabricated with the quarter-micron CMOS technology using shallow trench isolation and titanium salicide. It is shown that the magnitude of corner leakage component is more than two orders of magnitude larger than those of areal and peripheral leakage components in silicided p/sup +/-n junctions at all temperature. The corner leakage component will be more and more important as the active area gets smaller in sub-quarter-micron devices.

Effect of Crack Propagation Directions on the Interlaminar Fracture Toughness of Carbon/Epoxy Composite Materials

The interlaminar fracture toughness of carbon/epoxy composite materials has been studied under tensile and flexural loading using width-tapered double cantilever beam (WTDCB) and end-notched flexure (ENF) specimens. This study experimentally examines the effect of various interfacial ply orientations, α (0°, 45° and 90°) and crack propagation directions, θ (0°, 15°, 30° and 45°) in terms of the critical strain energy release rate. Twelve differently layered laminates were investigated. The fracture energy is deduced from the data according to the compliance method and beam theory. Beam theory is used to analyze the effect of crack propagation direction. The geometry and lay-up sequence of specimens are designed to probe various conditions such as skewness parameter and beam volume. Results show that fiber bridging occurred due to non-midplane crack propagation; this causes the difference in fracture energy calculated by both methods. For the construction of safer and more reliable composite structures, we obtain the optimal stacking sequence from the initial fracture energy in each mode.

Interlaminar fracture and low-velocity impact of carbon/epoxy composite materials

The interlaminar fracture and the low-velocity impact behavior of carbon/epoxy composite materials have been studied using width-tapered double cantilever beam (WTDCB), end-notched flexure (ENF), and Boeing impact specimens. The objectives of this research are to determine the essential parameters governing interlaminar fracture and damage of realistic laminated composites and to characterize a correlation between the critical strain energy release rates measured by interlaminar fracture and by low-velocity impact tests. The geometry and the lay-up sequence of specimens are designed to probe various conditions such as the skewness parameter, beam volume, and test fixture. The effect of interfacial ply orientations and crack propagation directions on interlaminar fracture toughness and the effect of ply orientations and thickness on impact behavior are examined. The critical strain energy release rate was calculated from the respective tests: in the interlaminar fracture test, the compliance method and linear beam theory are used; the residual energy calculated from the impact test and the total delamination area estimated by ultrasonic inspection are used in the low-velocity impact test. Results show that the critical strain energy release rate is affected mainly by ply orientations. The critical strain energy release rate measured by the low-velocity impact test lies between the mode I and mode II critical strain energy release rates obtained by the interlaminar fracture test.

Effects of nitrogen implantation in silicon for shallow p+-n junction formation

This letter will present the effects of nitrogen implantation on shallow p+-n junction formation in silicon. The p+-n junctions fabricated at different implantation conditions and heat budgets were characterized by secondary ion mass spectroscopy, current–voltage and capacitance–voltage measurements, and analyzed by transport of ions in matter simulation. The capacitance–voltage measurements of nitrogen implanted samples revealed the one-sided abrupt junction properties, and the current–voltage measurements indicated the shallow junction characteristics due to boron diffusion suppression by nitrogen. The activation energy is about 0.39 eV for temperatures below 80 °C, and its dominant leakage mechanism is phonon-assisted tunneling. At a reverse bias of −3 V, the leakage current density was 5.217×10−8 A/cm2 at −3 V, which is comparable to that of a conventional p+-n junction.

Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging

Time delay, /spl tau//sub D/ due to MLM is systematically characterized in circuit operating conditions. Novel utilization of simple test patterns is shown to enable: (a) separation of pure charging and drift-and-charging contributions to /spl tau//sub D/, hence, (b) fast and accurate quantification of /spl tau//sub D/ in the limit of superconducting metal lines or low temperature operation, and (c) dynamic extraction of MLM parameters and their contribution to /spl tau//sub D/.

Characterization of crosstalk-induced noise for 0.18 /spl mu/m CMOS technology with 6-level metallization using time domain reflectometry and S-parameters

Crosstalk-induced noise of 0.18 /spl mu/m CMOS Technology is characterized using time domain reflectometry and scattering parameters. The interconnect lines are quantitatively modeled in RF range, whose accuracy was verified with the use of TDR data and its comparison with HSPICE simulation. The modeled interconnect line is used to simulate comprehensively crosstalk-induced noise voltage in various real routing environments using HSPICE. The crosstalk voltage exhibited a strong dependence on line width rather than line space.

Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits

In this paper the dependence of interconnect line-induced delay time on the repeater size is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as repeater size increases. However there exists a point where the delay time becomes minimum when both of resistance and capacitance of interconnect line becomes larger than those of transistor. The optimum repeater size is obtained using an analytic equation and the experimental results showed good agreement with the calculation.

Comparative study of several anti-punchthrough designs for buried channel PMOSFET

As CMOS technology is scaled down, buried channel (BC) PMOS has been replaced by surface channel (SC) PMOS due to the poor short channel effect (SCE) in BC PMOS. Until now, however, BC PMOS has been widely used even in deep submicron CMOS devices because ofits advantage of simple fabrication process, no boron penetration, high driving capability due to no gate depletion, and higher mobility compared with SC PMOS. Several approaches have been proposed to suppress SCE in BC PMOS. A 0.15/spl mu/m single gate CMOS was reported using the conventional punchthrough stopper by arsenic implantation. A tilt implanted punchthrough stopper structure by using phosphorous or arsenic implantation was also proposed. However, these techniques have the disadvantage of insufficient anti-punchthrough or low current drivability. In this paper, Double Arsenic Punchthrough Stopper (DAPS) is proposed and compared with other structures. The DAPS is formed by arsenic implantation before and after the gate definition to improve both SCE and current drivability for BC PMOS.

Impact of Nitrogen Implantation in Lightly Doped Drain (NIL) on Deep Sub-Micron CMOS Devices

In this study, we investigate the device characteristics of lightly doped drain (LDD) metal-oxide-semiconductor field effect transistors (MOSFETs) with nitrogen implantation in the gate overlapped LDD region. As expected, the hot carrier lifetime under drain avalanche hot carrier (DAHC) stress condition is sufficiently improved in nMOSFETs with nitrogen implantation as part of the LDD (NIL) technique. However, the nitrogen-enhanced short channel effect is observed. The function of nitrogen atoms in pMOS devices has theopposite characteristic. In addition, the effective channel lengths shift in opposite directions in nMOSFET and pMOSFET. Off-state currents of NIL nMOSFET are degraded, resulting in the deterioration of the short channel length margin characteristic, while the short channel length margin is improved in NIL pMOSFET.