Tom Aton

Cosmic ray neutron induced upsets as a major contributor to the soft error rate of current and future generation DRAMs

The system soft error rate (SSER) of 4M/16M DRAMs has been shown to be dependent on the cosmic ray neutron flux. A simple model and accelerated soft error rate (ASER) measurements made with an intense, high energy neutron beam support this result. The model predicts that cosmic ray neutron induced soft errors will become important at the 64M DRAM generation and beyond.

Accurate measurements of small charges collected on junctions from alpha particle strikes using an accelerator-produced microbeam

We describe an accelerator-based system for accurate experiments of alpha particle strikes on integrated circuits. It produces a high-flux, micron-dimensioned collimated beam in air. High speed blanking controls the arrival time and number of alphas. We accurately measure the small alpha-generated charges that collect on junctions using novel test structures and measure SRAM soft error rates. The test structure results are compared to results from our fast alpha-strike simulator.

Process window and interlayer aware OPC for the 32-nm node

Pushing optical microlithography towards the 32nm node requires hyper-NA immersion optics in combination with advanced illumination, polarization, and mask technologies. Novel approaches in model-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) optimization are required to not only produce correct feature shapes at the nominal process condition but also to maintain edge placement tolerances within spec limits under process variations in order to ensure a finite process window. In addition, it is becoming increasingly important to consider interactions between multiple layers when performing correction in order to ensure electrical viability. In this paper we discuss the application of a model based process-window-aware and interlayer-aware integrated OPC system on 32nm node patterns. Process window awareness will be demonstrated for main feature correction by taking into account image-based modeling at multiple defocus and dose conditions. In addition, interlayer-awareness will be demonstrated by correction that takes into account the effects of active width on gate CD and of contact overlap with metal, gate, and active. The results show an improvement over non-aware OPC in gate CD control, in contact overlap, and in overall process margin. In addition, PW aware correction is demonstrated to prevent potential catastrophic failures at extreme PW conditions.

Variations in timing and leakage power of 45nm library cells due to lithography and stress effects

We have conducted a study of context-dependent variability for cells in a 45nm library, including both lithography and stress effects, using the Cadence Litho Electrical Analyzer (LEA) software. Here, we present sample data and address a number of questions that arise in such simulations. These questions include identification of stress effects causing context dependence, impact of the number of contexts on the results, and combining lithography-induced variations due to overlay error with context-dependent variations. Results of such simulations can be used to drive a number of corrective and adaptive actions, among them layout modification, cell placement restrictions, or optimal design margin determination.

OPC on real-world circuitry

In the face of Moores Law, the lithographic community is finding increasing pressure to do more with less. More, in the sense that lithographers are expected to use an exposure wavelength lambda that is shrinking at a slower rate than the critical dimensions (CDs) of devices. This has resulted in the introduction of complicated Resolution Enhancement Technology (RET) schemes. Less, in the sense that the competitive marketplace has resulted in shortened development cycles. These shortened development times mean that lithography and RET teams are often expected to demonstrate first pass success with increasing complex lithographic solutions. Unfortunately, first silicon on product prototypes may reveal deficiencies in an OPC infrastrcuture which had been developed using only research and development (R&D) testdie. The primary cause of these deficiencies is that the development and test-structure layouts frequently lack the 2D complexity of real circuitry. OPC models and lithography R&D traditionally compensate well for failures and marginal sites on the simple patterns of R&D testdie. The more complex geometries of real layouts frequently present new challenges. Here, we describe a program initiated at TI to add a complex pattern to the very first test reticle generated for a new technology node. This pattern is auto-generated and includes a random combination of representive circuits at the design rule for that node. OPC is applied to the pattern almost immediately after layout. The distribtion of printed features and marginal sites can then be identified early using simulation. Scanning Electron Microscope (SEM) images of resist and post-etch features can further identify sites requiring changes once reticles are received. We have shown that this early OPC R&D on complex geometries can prevent several OPC revision cycles and enable faster volume yield ramp.

Ion beam studies of events typical of soft errors in semiconductor memories

Abstract A fast ion microbeam has been used to study phenomena associated with soft errors in semiconductor memories. A spatially small beam with a fast blanking system is used to study both alpha particle and heavy ion strikes. The heavy ion strikes are typical of the recoil from cosmic-ray-generated neutrons. Charge collection and static RAM error-rate experiments are discussed.

Direct measurement for SOI and bulk diodes of single-event-upset charge collection from energetic ions and alpha particles

We describe experiments on charge collection from fluorine ions striking ICs and compare with the collection from alpha particles. The fluorine ion strikes are similar to the energetic heavy ions produced when cosmic-ray-generated neutrons collide with silicon nuclei in an IC. The typical measured charge collection is 10 fC for alpha particles and greater than 100 fC for fluorine ions in bulk diodes. For fluorine ions hitting silicon-on-insulator (SOI) diodes, the charge collection is typically less than 9 fC.

Design and performance of SOI pass transistors for 1 Gbit DRAMs

Both partially and fully depleted NMOS pass transistors were designed and fabricated on SIMOX substrates. Using a p+ gate design, V/sub th/=1 V and I/sub off/<1 fA//spl mu/m was achieved on ultra thin film SOI pass transistors. With less than 1 fA//spl mu/m off-state leakage, the SOI pass transistor provides excellent DRAM cell retention time and low stand-by power. The pass transistors junction voltage decay after precharge is much slower on the thin film SOI than on thicker film SOI. In addition, the SOI pass transistors were found to have higher DRAM charging efficiency than the bulk pass transistor due to the elimination of the body effect. The higher charging efficiency of SOI pass transistors allows a reduction in the word line voltage during the charging state, avoiding the need for the usual boosting of the DRAM word line voltage, thereby increasing the gate oxide integrity and decreasing the active power.

Dual-mask model-based proximity correction for high-performance 0.10-μm CMOS process

Selective strong phase shift mask techniques, whereby a phase-shift mask exposure is followed by a binary mask exposure to define a single pattern, present unique capabilities and problems. First, there is the proper exposure balance and alignment of the two masks. Second, there is the challenge of performing optical proximity correction that will account for two overlaying exposure models and masks. This is further complicated by the need to perform multiple biasing and adjustments that are often required for development processes. In this paper, we present results for applying a new OPC correction technique to a dual exposure binary and phase-shift mask that have been used for development of 100 nm CMOS processes. The correction recipe encompasses two models that were anchored to optimized processes (exposure, NA, and ?). The correction to the masks also utilized boolean techniques to perform selective biasing without destroying the original hierarchical structure. CMOS technology utilizes isolation with pitches of active device regions below 0.4 ?m. The effective gate length on silicon is in the range of 0.08 to 0.18 ?m. Patterning of trench openings and gate regions are accomplished using deep-UV lithography.

Ion beam induced charge collection (IBICC) from integrated circuit test structures using a 10 MeV carbon microbeam

As future sizes of Integrated Circuits (ICs) continue to shrink the sensitivity of these devices, particularly SRAMs and DRAMs, to natural radiation is increasing. In this paper, the Ion Beam Induced Charge Collection (IBICC) technique is utilized to simulate neutron-induced Si recoil effects in ICS. The IBICC measurements, conducted at the Sandia National Laboratories employed a 10 MeV carbon microbeam with 1pm diameter spot to scan test structures on specifically designed ICS. With the aid of layout information, an analysis of the charge collection efficiency from different test areas is presented. In the present work a 10 MeV Carbon high-resolution microbeam was used to demonstrate the differential charge collection efficiency in ICS with the aid of the IC design Information. When ions strike outside the FET, the charge was only measured on the outer ring, and decreased with strike distance from this diode. When ions directly strike the inner and ring diodes, the collected charge was localized to these diodes. The charge for ions striking the gate region was shared between the inner and ring diodes. I The IBICC measurements directly confirmed the interpretations made in the earlier work.