Jerry G. Fossum

Anomalous leakage current in LPCVD PolySilicon MOSFET's

The anomalous leakage current ILin LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of ILon the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce IL, and indicates when the back-surface leakage component is significant.

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.

Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's

Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible. >

Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs

A compact physics-based quantum-effects model for symmetrical double-gate (DG) MOSFETs of arbitrary Si-film thickness is developed and demonstrated. The model, based on the quantum-mechanical variational approach, not only accounts for the thin Si-film thickness dependence but also takes into account the gate-gate charge coupling and the electric field dependence; it can be used for FDSOI MOSFETs as well. The analytical solutions, verified via results obtained from self-consistent numerical solutions of the Poisson and Schrodinger equations, provide good physical insight with regard to the quantization and volume inversion due to carrier confinement, which is governed by the Si-film thickness and/or the transverse electric field. A design criterion for achieving beneficial volume-inversion operation in DG devices is quantitatively defined for the first time. Furthermore, the utility of the model for aiding optimal DG device design, including exploitation of the volume-inversion benefit to carrier mobility, is exemplified.

Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup +/ and p/sup +/ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight pertaining to the design of DG devices with channel lengths of 50 nm and less.

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

Large differences in the experimentally observed strain-induced threshold-voltage shifts for uniaxial and biaxial tensile-stressed silicon (Si) n-channel MOSFETs are explained and quantified. Using the deformation potential theory, key quantities that affect threshold-voltage (electron affinity, bandgap, and valence band density of states) are expressed as a function of strain. The calculated threshold-voltage shift is in agreement with uniaxial wafer bending and published biaxial strained-Si on relaxed-Si/sub 1-x/Ge/sub x/ experimental data , and explains the technologically important observation of a significantly larger (>4x) threshold-voltage shift for biaxial relative to uniaxial stressed MOSFETs. The large threshold shift for biaxial stress is shown to result from the stress-induced change in the Si channel electron affinity and bandgap. The small threshold-voltage shift for uniaxial process tensile stress is shown to result from the n/sup +/ poly-Si gate in addition to the Si channel being strained and significantly less bandgap narrowing.

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/</spl sim/4 nm in nMOSFETs with {110}-Si surfaces and in pMOSFETs, will strongly influence DG CMOS design and scalability.

A physical model for the dependence of carrier lifetime on doping density in nondegenerate silicon

Abstract A theoretical model that describes the dependence of carrier lifetime on doping density, which is based on the equilibrium solubility of a single defect in nondegenerately doped silicon, is developed. The model predictions are consistent with the longest measured hole and electron lifetimes reported for n -type and p -type silicon, and hence imply a possibly “fundamental” (unavoidable) defect in silicon. The defect is acceptor-type and is more soluble in n -type than in p -type silicon, which suggests a longer fundamental limit for electron lifetime than for hole lifetime at a given nondegenerate doping density. The prevalent, minimum density of the defect, which defines these limits, occurs at the processing temperature below which the defect is virtually immobile in the silicon lattice. The analysis reveals that this temperature is in the range 300–400°C, and thus emphasizes, when related also to common non-fundamental defects, the significance of low-temperature processing in the fabrication of silicon devices requiring long or well-controlled carrier lifetimes.

Short-channel effects in SOI MOSFETs

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed. >

Theory of grain-boundary and intragrain recombination currents in polysilicon p-n-junction solar cells

The physics controlling recombination in polysilicon p-n-junction solar cells is described. Analytic models characterizing this recombination, whose parameters can be related directly to experiment, are developed. The analysis reveals that, in general, the description of intragrain and grain-boundary recombination in a polysilicon solar cell requires the solution of a nonlinear three-dimensional boundary-value problem. Cases of practical interest for which this problem is tractable are discussed. The analysis predicts an\exp (qV/2kT)dependence (the reciprocal slope factor is exactly two) for carrier recombination at a grain boundary within the junction space-charge region of a nonilluminated, forward-biased cell. This result, and others of the analysis, are consistent with preliminary experimental data.