Murshed M. Chowdhury

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.

Physical insights on design and modeling of nanoscale FinFETs

An array of measured device data, a numerical device simulator, and a process/physics-based compact model are used to gain new and important physical insights on nanoscale FinFETs with undoped thin-fin bodies. The insights, which include unavoidable/needed gate underlap, bias-dependent effective channel length, and non-ohmic fin-extension voltage drops, reveal the significance of gate positioning on, and source/drain doping profile in, the thin fin, and imply novel compact modeling that will be needed for optimal design of nonclassical CMOS circuits.

Physical insights on electron mobility in contemporary FinFETs

Calibration of a physics/process-based model for double-gate (DG) MOSFETs to contemporary nanoscale undoped n-channel DG FinFETs reveals that 1) significant densities of source/drain donor dopants readily diffuse to the ultrathin (fin) body/channel, even with relatively long fin extensions, degrading electron mobility at low/moderate levels of inversion-carrier density (N/sub inv/), 2) surface-roughness scattering of electrons is less severe at the {110} silicon-fin surfaces than anticipated, and 3) strong-inversion electron mobility is quite high (e.g., /spl cong/290 cm/sup 2//V/spl middot/s at N/sub inv/=10/sup 13/ cm/sup -2/), being about three times higher than that in contemporary bulk-Si MOSFETs.

Carrier Mobility/Transport in Undoped-UTB DG FinFETs

A process/physics-based double-gate (DG) MOSFET model (UFDG), which includes a quantum-based carrier mobility model, is used to examine carrier transport in undoped ultrathin-silicon bodies/channels. The model predicts for {100}-surface devices, in accord with measurements, effective electron and hole mobilities that are dramatically higher than those in contemporary bulk-Si MOSFETs at the same integrated inversion-carrier density. Calibration of UFDG to undoped p- and n-channel DG FinFETs yields consistent results, showing very high mobilities in contemporary FinFETs, implying relatively smooth {110} fin-sidewall surfaces, and giving new insights on electron and hole mobilities in DG MOSFETs with {110} versus {100} surfaces. The calibrated model is used to simulate 17.5-nm DG FinFETs with midgap gates, predicting ballistic-like currents and, hence, suggesting that strained-Si channels are not needed for mobility enhancement in these nonclassical devices

Study of undoped channel FinFETs in active rail clamp ESD networks

In this paper we investigate state-of-the-art undoped channel FinFETs and FinDiodes with an emphasis on I/O and ESD applicability. Utilizing electrical characterization data, 3D TCAD, and a compact model, we demonstrate that FinFETs and FinDiodes exhibit a very appealing combination of high breakdown voltage and low Ioff for I/O and ESD protection circuit applications.

Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts

We demonstrate a dual silicide integration on a SOI CMOS platform with robust low-resistance PtSi PMOS contacts. Compared to NiSi, the specific contact resistivity is reduced in PtSi contacts to p-type Si and increased in contacts to n-type Si. PMOS linear and saturation drive current enhancements of 6% and 9%, respectively, were achieved with PtSi relative to baseline NiSi source/drain contacts.

Insights on Carrier Mobilities and Transport in Contemporary DG FinFETs

In this paper we calibrate our process/physics-based DG MOSFET model (UFDG (Fossum, et. al., 2004)) to contemporary DG FinFETs, and examine carrier mobilities in the undoped UTBs. The calibrated model is also used to give interesting insights on carrier transport in nanoscale DG FinFETs that contradict ITRS projections