Vishal P. Trivedi

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/</spl sim/4 nm in nMOSFETs with {110}-Si surfaces and in pMOSFETs, will strongly influence DG CMOS design and scalability.

Suppression of corner effects in triple-gate MOSFETs

The abnormal corner effects on channel current in nanoscale triple-gate MOSFETs are examined via two-dimensional (2-D) numerical simulations and quasi-2-D analysis. Heavy body doping [for threshold voltage (V/sub t/) control with a polysilicon gate] is found to underlie the effects, which can hence be suppressed, irrespective of the shape of the corners, by leaving the body undoped, and relying on a metal gate with proper work function for V/sub t/ control. Short-channel effects tend to ameliorate the corner effects, but the need for ad hoc suppression remains.

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.

Physical insights on design and modeling of nanoscale FinFETs

An array of measured device data, a numerical device simulator, and a process/physics-based compact model are used to gain new and important physical insights on nanoscale FinFETs with undoped thin-fin bodies. The insights, which include unavoidable/needed gate underlap, bias-dependent effective channel length, and non-ohmic fin-extension voltage drops, reveal the significance of gate positioning on, and source/drain doping profile in, the thin fin, and imply novel compact modeling that will be needed for optimal design of nonclassical CMOS circuits.

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

Nanoscale FD/SOI CMOS: thick or thin BOX?

The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.

Pragmatic design of nanoscale multi-gate CMOS

Three-dimensional numerical device simulations are done to gain physical insights on multi-gate FinFETs, which portend the infeasibility of nanoscale triple-gate CMOS, and process/physics-based device/circuit simulations are done to check the concept of pragmatic nanoscale double-gate CMOS design, showing encouraging performance projections near the end of the SIA 2003 ITRS (2003).

An RCP Packaged Transceiver Chipset for Automotive LRR and SRR Systems in SiGe BiCMOS Technology

We present a transceiver chipset consisting of a four channel receiver (Rx) and a single-channel transmitter (Tx) designed in a 200-GHz SiGe BiCMOS technology. Each Rx channel has a conversion gain of 19 dB with a typical single sideband noise figure of 10 dB at 1-MHz offset. The Tx includes two exclusively-enabled voltage-controlled oscillators on the same die to switch between two bands at 76-77 and 77-81 GHz. The phase noise is -97 dBc/Hz at 1-MHz offset. On-wafer, the output power is 2 × 13 dBm. At 3.3-V supply, the Rx chip draws 240 mA, while the Tx draws 530 mA. The power dissipation for the complete chipset is 2.5 W. The two chips are used as vehicles for a 77-GHz package test. The chips are packaged using the redistribution chip package technology. We compare on-wafer measurements with on-board results. The loss at the RF port due to the transition in the package results to be less than 1 dB at 77 GHz. The results demonstrate an excellent potential of the presented millimeter-wave package concept for millimeter-wave applications.

Bulk inversion in FinFETs and implied insights on effective gate width

Relative values of on-state current in undoped-body double-gate (DG) and triple-gate (TG) FinFETs are examined via three-dimensional numerical device simulations. The simulation results reveal significant bulk inversion in the fin bodies, which limits the benefit of the third (top) gate in the TG FinFET and which negates the utility of the commonly defined effective gate width (W/sub eff/=2h/sub Si/+w/sub Si/). Even the concept of W/sub eff/ for the TG FinFET is invalidated, but the proper W/sub eff/ for the DG FinFET is defined. Physical insights attained from the simulations further solidify our notion, based previously on gate layout-area inefficiency, that the third gate is neither desirable nor beneficial.