Zhichao Lu

Physical Insights on BJT-Based 1T DRAM Cells

The basic operation of BJT-based floating-body 1T DRAM cells on SOI is analyzed with supportive numerical device simulation. Extreme sensitivity of the charging process (write ldquo1rdquo) to the offset (Deltat WB) between the word-line and bit-line voltage pulses is revealed and explained. The necessity of a positive Deltat WB for successful write ldquo1rdquo is related to establishing a high gate capacitance, which is the predominant charge-storage element in the BJT-based cell. Such charging underlies why a fully depleted (FD) cell, e.g., a FinFET, can work for BJT-based DRAM, without an independent bias for accumulation charge that is necessary in conventional FD-MOSFET DRAM cells for charge storage and data sensing. Furthermore, a bulk-accumulation effect in the BJT-based DRAM cell is revealed and described. It undermines the BJT operation and leads to ineffective charging and significant loss of sense margin when the cell body thickness is scaled.

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

A Simplified Superior Floating-Body/Gate DRAM Cell

The basic concept of a simplified and easily manufacturable version of the two-transistor floating-body/gate DRAM cell (FBGC) is proposed and demonstrated via simulation and fabrication/experiment. Converting the charge-storage transistor (T1) to a gated diode enables easy and direct connection of its body to the gate of the sensing transistor in conventional planar SOI CMOS and in FinFET technologies, and also reduces the cell size. Numerical simulations show that the new cell can yield a much better signal margin and dissipate much less power than the one-transistor floating-body DRAM cells currently being assessed. A FinFET-based prototype of the new cell provides experimental corroboration of these features.

Short-Channel Effects in Independent-Gate FinFETs

A physics-based model is used to examine short-channel effects (SCEs) in undoped nanoscale independent-gate FinFETs, e.g., the MIGFET (L. Mathew, , Proc. IEEE Internat. SOI Conf., p. 187, 2004). Predicted current-voltage characteristics of MIGFETs in the single-gate mode show that the SCEs (threshold-voltage rolloff, subthreshold-swing degradation, and drain-induced barrier lowering) are actually less severe than those of the device in the double-gate mode. Insightful explanations of the results are given

A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time

A novel modification of our “2T” floating-body/gate DRAM cell is described and, via numerical simulations, shown to yield very long charge data retention times under worst-case conditions, as well as good memory performance (i.e., large signal margin and low operating power). Relatively low voltage operation is enabled, thereby implying good cell reliability as well.

Hot hole induced damage in 1T-FBRAM on bulk FinFET

The reliability of a one Transistor Floating Body Random Access Memory (1T-FBRAM) bulk FinFET cell using Bipolar Junction Transistor (BJT) programming is investigated. It is shown that hot holes generated by impact ionization create interface defects close to the drain and positively charged oxide traps, especially at high transverse electric field. These created defects degrade the cell endurance. Moreover, this degradation is enhanced for shorter channel devices and narrower fin widths, which would be a limitation for the scaling of floating body RAM.

Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories

A capacitorless DRAM cell, floating-body/gate cell (FBGC), is experimentally presented with planar partially depleted SOI CMOS technology. The specially designed gate/drain underlap and gate/source overlap of the first transistor enable long worst case retention time as well as the fast write speed. The operation power dissipation is dramatically reduced while maintaining high sense margin. In addition, FBGC demonstrates excellent endurance performance and nondestructive read operation.

BJT-Mode Endurance on a 1T-RAM Bulk FinFET Device

In this letter, endurance is investigated on one bulk FinFET transistor capacitorless random access memory, using the bipolar junction transistor (BJT) programming mode. For the first time, it is shown that endurance is an issue using the BJT-mode programming. The dominant degradation is due to the interface state generation by impact ionization used to write “1.” This degradation leads to the gate-induced drain leakage current increase, which results in shifts of the read state “0” current.

A Novel Two-Transistor Floating-Body Memory Cell

In this paper we propose a novel two-transistor (2T) FBC for DRAM applications that can yield much better signal margin and density, while offering other significant advantages over the 1T cell. The key features of the 2T FBC are demonstrated via process/physics-based device/circuit simulations, supported by numerical results.

An ultra-fast floating-body/gate cell for embedded DRAM

Floating-body DRAM cells (FBCs) on SOI are of interest because of integration problems associated with the large storage capacitor of nanoscale conventional 1T/ 1C DRAM. However, limitations on FBC speed, due to relatively slow write times governed by the usual impact-ionization or tunneling body-charging processes, preclude the application of most interest - embedded DRAM. We recently proposed a novel 2T (T1 and T2) FBC, i.e., a floating-body/gate cell (FBGC) , which enables design flexibility for optimizing performance. We present herein a new 2T design concept (FBGC4) that gives ultra-fast write times, in addition to good current-signal margin and long retention times, and thus enables the embedded-DRAM application. Further, low power and good reliability are implied because of low-voltage operation afforded by FBGC4.