Jessy Bustos

Optimization of block copolymer self-assembly through graphoepitaxy: A defectivity study

In this paper we report a synoptic methodology to evaluate and optimize the long-range order induced by graphoepitaxy of block copolymer (BCP) self-assembly. The authors focus the study on a BCP that produces hexagonally packed arrays of cylinders oriented perpendicular to the substrate with the copolymer film thickness greater than the trench depth. Prepatterned structures used in the graphoepitaxy approach have been generated by e-beam lithography on a commercial hydrogen silesquioxane resist. A suitable surface modification was accomplished by grafting a random polystyrene-r-poly(methyl methacrylate) copolymer on the prepatterned surfaces. The polystyrene-b-poly(methyl methacrylate) was spin-coated and annealed in order to generate the desired self-assembly. Since the self-assembly process is based on a thermodynamic mechanism, the induced defectivity needs to be reassessed with respect to the standard lithographic process. Using the cylinder center coordinates, a Delaunay triangulation is performed to find the nearest neighbors. This triangulation enables us to easily locate the disclinations which are characterized by having a number of nearest neighbors different from six. Thus, the number of defects can be quantified precisely. Additionally, this methodology affords an accurate evaluation of both the optimum mesa and trench critical dimensions yielding defect-free surfaces and may be extended to monitor the robustness of the BCP directed self-assembly process. Such diagnostics are critical in the implementation of large scale industrial processes.

High-Performance High-

By introducing high-K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35 nm CMOS devices that exhibit high-performance drive currents (2230/1000 muA/ mum for N/ P at Vd = 1.2 V), low off-state currents (3/5 nA/mum), and excellent subthreshold characteristics. When benchmarked with other published multigate data, the results presented in this paper are proved to be among the best and underline the potential of planar self-aligned GAA devices for the 32 nm technology and below. In particular, it is demonstrated that an optimized supply voltage can bring a significant improvement in circuit time delay and power when using GAA devices.

K

Among the different next generation lithography techniques, multibeam may arise as a cost effective solution to pattern sub-22nm technological nodes. A low LWR is required to keep downscaling. In this study, capability of producing low LWR 32/32nm L/S patterns with two different ebeam tools was evaluated. One state-of-the-art single variable shapedbeam (50kV) VISTEC SB3054 and a multiple Gaussian beam MAPPER ASTERIX pre-alpha tool (5kV) are used. Thanks to the great flexibility of e-beam lithography, exposure of biased designs in which the exposed area is reduced is carried out. Such exposure strategy showed a great effectiveness to lower LWR (down to around 3.0nm). To reduce further LWR some post litho-treatments such as thermal processing, plasma treatments and UV treatments are used on patterns exposed with VISTEC SB3054. A combination of a biased exposure and post-litho treatments reduced initial 4.8nm LWR down to 2.8nm (41.7% reduction). Once complete the LWR reduction protocol will be transferred on MAPPER exposures.

/Metal Planar Self-Aligned Gate-All-Around CMOS Devices

Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multiworkfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

Line width roughness reduction strategies for patterns exposed via electron beam lithography

This paper deals with a new compensation method to insure Micro-Electro-Mechanical (MEM) resonators frequency accuracy. We report new results of modeling, fabrication and characterization of MEM resonators frequency compensated fulfilling industry requirements respect to CMOS compatibility and collective correction. Both clamped-clamped beam and bulk mode resonators presenting compensation holes are treated.